swapnilm Posted March 18, 2013 Report Share Posted March 18, 2013 Hello All, I am working on UVM. While trying to simulate my design, I am getting following error:- Fatal: (SIGSEGV) Bad handle or reference. The code of the test.sv is given below:- class test1 extends uvm_test; `uvm_component_utils(test1) virtual dut_if dut_vi; env env_h; // env_h is a handle reference to env class //constructor by using keyword new function new(string name, uvm_component parent); super.new(name, parent); endfunction: new function void build_phase(uvm_phase phase); super.build_phase(phase); if( !uvm_resource_db#(virtual dut_if)::read_by_name("dut_ifs", "dut_vi", dut_vi, this)) `uvm_fatal("NOVIF", "No virtual interface set") uvm_config_db #(virtual dut_if)::set(this, "*", "dut_vi", dut_vi); endfunction: build_phase // task run_phase(uvm_phase phase); virtual task run(); seq_fixedno_pkts seq1; // seq1 = sequence1::type_id::create("seq1"); seq1 = new(); assert( seq1.randomize() ); //#100ns; //seq.start( env_h.agent_h.sequencer1_h ); // seq.start(env_h.agent_h.sequencer1_h.print()); seq1.start(env_h.agent_h.sequencer1_h) ; //.print(); // env_h.agent_h.sequencer1_h.print(); // #100ns; uvm_top.stop_request(); //stop_request() stops the sequences in the test. endtask: run endclass: test1 Basically the error is pointed at line seq1.start(env_h.agent_h.sequencer1_h) ; Can someone please put some line on this error. I am not able to understand why this error is coming. I have connected all the components properly. Any help is appreciated. Its urgent, so please give me some feedback on how to resolve it. Thanks, Quote Link to comment Share on other sites More sharing options...
omahesh Posted March 18, 2013 Report Share Posted March 18, 2013 Hi, According to your code, i guess the problem with the virtual interface and try to move all the virtual interface definitions to module top level testbench and perform uvm_config_db. hope it helps. thanks, mahee Quote Link to comment Share on other sites More sharing options...
swapnilm Posted March 18, 2013 Author Report Share Posted March 18, 2013 Hello Mahee, Thanks for your reply. The error actually points at the line :- seq1.start(env_h.agent_h.sequencer1_h) ; So how did you come to conclusion that the problem is with virtual interface? My guess was that the problem could be with the sequences, although I tried to make some changes in sequence's code but the Fatal Error is still there. I am not at all getting how to resolve this Fatal Error: (SIGSEGV) Bad handle or reference. Could you plz give little more elaboration/explanation on your suggestion? I would appreciate that. Thanks, Swapnil Quote Link to comment Share on other sites More sharing options...
fordinesh Posted March 19, 2013 Report Share Posted March 19, 2013 The env_h has to point to an env object. I don't see any object created for env in this test class. You have to create env in build phase or point the env_h handle to an existing handle somewhere in your testbench if already present. Quote Link to comment Share on other sites More sharing options...
swapnilm Posted March 19, 2013 Author Report Share Posted March 19, 2013 Hello fordinesh, you are so right. I missed creating the env object in build phase.I was actually looking more into sequence code. It removed the fatal error. Thanks. Its now printing the uvm_info msgs from scoreboard also. Thanks. Can you please tell me one more thing? I am actually trying to connect the driver directly to monitor through dut_if and blank DUT(having only uvm_info msg to print that its received the packet). Is there any other way to directly connect driver to monitor, without going into the DUT, in the dynamic environment, like through TLMs? Please give me some guidance. I appreciate it. Thanks, Swapnil Quote Link to comment Share on other sites More sharing options...
Hash Posted March 19, 2013 Report Share Posted March 19, 2013 As far as i know we connect using TLM's and not sure if there is any other way. TLM is nothing but a FIFO ,you read /write out of it Quote Link to comment Share on other sites More sharing options...
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