Range must be bounded by constant expressions

[ssingh]

I am trying to implement the following in systemverilog.

always_comb

begin

for(int i=0;i<=124;i=i+6)

begin

offset = DFF_data[ ((2*i)+1) : (2*i) ]; // Error !

data_output[i+offset]= data_input;

end

end

I get the following error in the line marked above: Range must be bounded by constant expressions. The error ocuurs beacuse of the use of "i" in defining the range of array DFF_data. But writing this without "i" seems impractical. I am using QuestaSim 10.1d. Has anyone come across such a situation?

Edited February 1, 2013 by ssingh

[dave_59]

Answer posted here: https://forum.verificationacademy.com/forum/verification-methodology-discussion-forum/systemverilog-and-other-languages-forum/29709-range-must-be-bounded-constant-exp