Jump to content

Questa 10.1 Simulator In UVM, Getting Lots of Errors

Recommended Posts

Hi all,

I am running my I2S Verification code in Questa 10.1. I am getting errors in every UVM_BASE_CLASSES.

I think, I have committed some mistakes in my Makefile. I have pasted an error and makefile below.

** Error: ../tb_uvm/i2s_xactn.sv(5): near "uvm_sequence_item": syntax error, unexpected IDENTIFIER

** Error: ../tb_uvm/i2s_xactn.sv(5): Error in class extension specification.


vlib work

vlog +acc -sv +incdir+$(UVM_HOME)/src $(UVM_HOME)/src/uvm_pkg.sv +define+UVM_NO_DPI -mfcu -f flist -l qsta.log

vsim -c +UVM_TESTNAME=i2s_base_test +UVM_VERBOSITY=UVM_FULL top -do "run -a;quit" -l lab6_simple_qsta.log

Please help me to solve this issue.


John Jacob

Link to comment
Share on other sites

  • 9 months later...

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...