enchanter

Thanks. That fix works.

When I play around with the factory/basic example from uvm-systemc-1.0-beta1, In the original example code, it prints the instance override information as below: UVM_INFO @ 0 s: reporter [RNTST] Running test ... UVM_INFO ../../../../src/uvmsc/factory/uvm_default_factory.cpp(1185) @ 0 s: reporter [UVM/FACTORY/PRINT] #### Print Factory Configuration (*) Instance Overrides: Requested Type Override Path Override Type -------------- ------------- ------------- gen top.e.gen1 mygen Type Overrides: Requested Type Override Type -------------- ------------- packet mypacket All types registered with the factory: 22 total Type Name --------- env gen mygen mypacket packet reg_rw top (*) Types with no associated type name will be printed as <unknown> But when I try to comments out the line in factory/basic/top.h (top::build_phase) as below: set_inst_override("e.gen1", "gen", "mygen"); // set_type_override("packet","mypacket"); I expect print factory configuration should still print the instance override but not the type override. But it doesn't print any override. UVM_INFO @ 0 s: reporter [RNTST] Running test ... UVM_INFO ../../../../src/uvmsc/factory/uvm_default_factory.cpp(1185) @ 0 s: reporter [UVM/FACTORY/PRINT] #### Print Factory Configuration (*) No instance or type overrides are registered with this factory All types registered with the factory: 22 total Type Name --------- env gen mygen mypacket packet reg_rw top (*) Types with no associated type name will be printed as <unknown>

Thanks Philipp. I will try it with gcc.

I am try to compile tlm1/bidir example from uvm-systemc-1.0-beta1 with SystemC 2.3.2 I got error as below and I have no idea what I have done wrong. ~/systemc/include/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_put_get_imp.h:87:7: error: inherited virtual base class 'sc_core::sc_interface' has private destructor class tlm_master_imp : ^ I have attached the full compile log comp.log

For the build issue, I think you can over CMake configure in SystemC to set library path to wherever you want.

Any plan to fix this build error on Mac OS? libtool: link: ar cru .libs/libmacros.a ar: no archive members specified usage: ar -d [-TLsv] archive file ... ar -m [-TLsv] archive file ... ar -m [-abiTLsv] position archive file ... ar -p [-TLsv] archive [file ...] ar -q [-cTLsv] archive file ... ar -r [-cuTLsv] archive file ... ar -r [-abciuTLsv] position archive file ... ar -t [-TLsv] archive [file ...] ar -x [-ouTLsv] archive [file ...] make[4]: [libmacros.la] Error 1 (ignored)

In installed uvm-systemc.pc file, it sets Libs to "-luvm". Should it be "-luvm-systemc"?

Saw the UVM-SystemC-1.0-beta1 download link, try to install it, but according to the INSTALL file, I can't find "configure" in the package. How could I install it?

That is a great news. Will this time add some examples about how to driving clock/reset signal as I ask in this post?

Thanks for the help. I did some digging too and I also thought it is becaused by the clock events. So I tried to use the set_timeout on that example which should finished in 100 NS. When I set the timeout to 30 NS, it killed the simulation at 30 NS as expected. But when I set it to 200 NS, the simulation will not finish. I haven't figure out why.

For UVM, it should not start the simulation by directly call sc_start() and sc_stop().

I played with scoreboard/basic example from uvm-systemc package, it finished simulation automatically: But when I try to add clock signal to the DUT and sc_main as below: dut.h #ifndef DUT_H_ #define DUT_H_ #include <systemc> class dut : public sc_core::sc_module { public: sc_core::sc_in<int> in; sc_core::sc_in<bool> clk; sc_core::sc_out<int> out; void func() { int val; val = in.read(); std::cout << sc_core::sc_time_stamp() << ": " << name() << " received value " << val << std::endl; std::cout << sc_core::sc_time_stamp() << ": " << name() << " send value " << val+1 << std::endl; out.write(val+1); } SC_CTOR(dut) : in("in"), out("out") { SC_METHOD(func); sensitive << clk.pos(); } }; #endif /* DUT_H_ */ sc_main.cpp #include <systemc> #include <uvm> #include "testbench.h" #include "dut.h" #include "vip_if.h" int sc_main(int, char*[]) { // instantiate the DUT sc_core::sc_time CLK_PERIOD(10, sc_core::SC_NS); sc_core::sc_clock clk("clk", CLK_PERIOD, 0.5); dut* my_dut = new dut("my_dut"); testbench* tb = new testbench("tb"); //uvm_config_db_options::turn_on_tracing(); vip_if* dut_if_in = new vip_if(); vip_if* dut_if_out = new vip_if(); uvm::uvm_config_db<vip_if*>::set(0, "tb.agent1.*", "vif", dut_if_in); uvm::uvm_config_db<vip_if*>::set(0, "tb.agent2.*", "vif", dut_if_out); my_dut->clk(clk); my_dut->in(dut_if_in->sig_data); my_dut->out(dut_if_out->sig_data); uvm::run_test(); return 0; } The simulation will not stop and I have to kill the process. scoreboard_basic.tar.gz2

I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals. I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish. So would someone let me know what's the right way to handle the clock and reset signals?

The SystemC 2.3.2 has been release, does anyone work on make it support the new version? And also supports modern C++ (11, 14, 17)?

I am learning the TLM example at_4_phase in the SystemC 2.3.1 package. But I don't know why there are 16 WRITE commands are generated by the traffic_generator? From my understanding, the m_transaction_queue is enqueue-ed twice. So I think it should only generate 2 commands then the queue should be empty. Why it generate 16 WRITE and 16 READ commands instread?