apfitch

I've just realised your clock declaration looks wrong. It should be (I think) sc_clock clk1("clk1", 10, SC_NS); regards Alan P.S. I highly recommend that the label should be identical to the instance name, it makes debugging easier.

I'm not sure exactly what you want to do - but I assume you want to connect the clock clk1 to the port popo_in. So in sc_main you need int sc_main (int argc, char *[] argv) { sc_signal<bool> popo_out; sc_clock clk1("clock1",10,0.5,5,true); popo_clk_gen pcg("pcg"); pcg.popo_out(popo_out); pcg.popo_in(clk1); sc_start(50,SC_NS); return 0; } You also need to trigger your SC_METHOD by making it sensitive to the port popo_in, For ease of understanding, I would rename the module "popo_clk_gen" to "popo_inverter" since it's just an inverter. regards Alan

There's a difference between a signal and a variable. A signal does have delta cycle behaviour - so when the clock changes, module 2 will read the current (before the change) value. With a plain C++ variable the result is undefined as you don't know which process will run first (the process in module 1 or the process in module 2) regards Alan

You need to set up the include path in your project (the path to systemc.h). You'll also need to set up the the library path to the systemc library at the same time (I assume you have built the library). You'll need to read the compiler documentation to find out how to do that, regards Alan

Just write a destructor and release the memory there (it's only C++). If you dynamically create modules, you can probably get away without releasing the memory as the module structure does not change after elaboration, and will hopefully disappear when the program ends. Alan

No, it's not required to use separate .h and .cpp with C++. You make the .cpp files - .h files are just included. If I understand your last question - you can put all your code in one .cpp file regards Alan

On Windows, Visual C++ is good - it will prompt you for method names when typing etc. On Linux, I prefer a plain text editor. There are also commercial tools if you have lots of money regards Alan

1. Is an instance of the class top with the instance name top1 and the module name "Top1". 2. top (sc_module_name name) : sc_module(name) is the class constructor, pushing the module name into the base class, sc_module. It is mandatory for all modules to be given a string name, and this name is stored in the base class sc_module. regards Alan

There's a tutorial on http://www.doulos.com/knowhow/systemc which is quite RTL like. regards Alan P.S. If you don't know C++, expect to find SystemC difficult :-)

You need to follow the instructions in the INSTALL notes for Visual C++. (I assume Visual Basic is a typo). The install notes are inside the SystemC distribution. You need to set up include paths, and library paths. You will also encounter an error with Visual C++ 2013 - the solution is described here: http://forums.accellera.org/topic/1713-problem-while-trying-to-build-systemclib/?hl=%2Bvisual+%2B2013 This will be fixed in the 2.3.1 release of SystemC, regards Alan

Hi, I compiled your code, and eventually spotted that you'd instanced the memory in sc_main, not the test bench. If you instance the testbench, and fix a few other things, it works. #ifndef Memory_H #define Memory_H #include "systemc.h" SC_MODULE(my_memory) { sc_in <bool> clk; sc_in <sc_bv<12> > address; sc_in <sc_bv<16> > datain; sc_out <sc_bv<16> > dataout; sc_in <bool> write_en; sc_signal <sc_bv<16> > mem[4096]; void read () { while (true) { wait(); dataout.write(mem[address.read().to_uint()]); } } void writ() { while (true) { wait(); if( write_en.read() == true ) { mem[address.read().to_uint()]=datain.read(); cout << "Writing to address " << address << " data " << datain << endl; } } } SC_CTOR(my_memory) : clk("clk"), address("address"), datain("datain"), dataout("dataout"), write_en("write_en") { for(int i = 0; i <= 4095;i++) mem[i].write(0); SC_THREAD(writ); sensitive<<clk.pos(); SC_THREAD(read); sensitive<<address; } }; #endif #ifndef memory_tb_H #define memory_tb_H //#include "memory.h" #include "systemc.h" SC_MODULE(memory_tb) { sc_signal <bool> clk_t; sc_signal <sc_bv<12> > address_t; sc_signal <sc_bv<16> > datain_t, dataout_t; sc_signal <bool> write_t; void apply_clk() { for(int i = 0;i < 1000;i+=5) { clk_t = false; wait(5,SC_NS); clk_t = true; wait(5,SC_NS); } wait(); } void apply_write() { write_t = true; datain_t.write(5); wait(9,SC_NS); wait(2,SC_NS); write_t = false; wait(2,SC_NS); datain_t.write(7); wait(20,SC_NS); write_t = false; cout << "read at " << sc_time_stamp() << " " << dataout_t << endl; // printf("read at 32ns : %d\n",dataout_t.read().to_uint()); wait(10,SC_NS); cout << "read at " << sc_time_stamp() << " " << dataout_t << endl; // printf("read at 42ns : %d\n",dataout_t.read().to_uint()); wait(10,SC_NS); cout << "read at " << sc_time_stamp() << " " << dataout_t << endl; wait(); } void apply_address() { address_t.write(0); wait(10,SC_NS); address_t.write(1); wait(10,SC_NS); address_t.write(2); wait(10,SC_NS); address_t.write(1); wait(10,SC_NS); address_t.write(2); wait(10,SC_NS); address_t.write(0); wait(10,SC_NS); wait(); } my_memory *mem; SC_CTOR(memory_tb) : clk_t("clk_t"), address_t("address_t"), datain_t("datain_t"), dataout_t("dataout_t"), write_t("write_t") { SC_THREAD(apply_clk); SC_THREAD(apply_address); SC_THREAD(apply_write); mem = new my_memory("pouya"); (*mem).clk(clk_t); (*mem).address(address_t); (*mem).datain(datain_t); (*mem).dataout(dataout_t); (*mem).write_en(write_t); } }; #endif int sc_main(int argc, char ** argv) { printf("Starting the simulation ...\n"); memory_tb top("CUT"); sc_start(1000, SC_NS); return 0; } regards Alan

The bad solution is to increase the stack size. From memory, there's an option in Visual C++ like /Zm which affects stack size. The good solution is to avoid allocating large amounts of memory on the heap, in other words use dynamic memory for your memory array. You can do this by making the array dynamically allocated memory, or as I said above, just use std::vector to hold the data, regards Alan

There's a number of things that I notice. As Dakupoto says, you need infinite loops in your SC_THREADs of your memory model, otherwise they will only run once at time zero. You should use sc_main() in your top level (not main()). All SystemC processes run at time zero independently of their sensitivity (unless you use dont_initialize()). That means that void my_memory::writ() will run at time zero with an undefined address value. I suggest checking the address value for out-of-range values before using it. Declaring a large sc_signal array sc_signal<sc_bv<16> mem [4096] may cause stack problems - I don't think that needs to be an sc_signal, so why not use std::vector instead (which uses dynamically allocated/ heap memory and so can't cause stack overflow). I always use named port binding as positional port binding is error-prone, so personally I wouldn't write (*mem)(clk_t,address_t,content_t,write_t); though of course it is legal. regards Alan

That message is saying that there's no overloaded sc_trace for std::string. One option might be to copy the string into an sc_bv and trace that (as there is an sc_trace for sc_bv). The list of built-in sc_trace functions is in the 1666-2011 standard, regards Alan P.S. I expect that free waveform viewers like gtkwave won't be able to display strings on the waveforms anyway.

Can you post the exact code that crashes? regards Alan

Can you make a very small test case and see if that crashes? In your post title you say "unhandled exception for all codes", so does #include "systemc.h" int sc_main(int argv, char ** argv) { cout << "hallo world" << endl; return 0; } Does that crash? If so what exactly is the error? regards Alan

read() is a method of SystemC classes such as sc_signal and sc_in. info is just a data member of your struct. So presumably you need A.read().info As the error says class sc_core::sc_in<MyType> has no member named info because info is a member of MyType, not a member of sc_in<MyType> regards Alan

See http://www.doulos.com/knowhow/systemc/faq/#q1 regards Alan

You've declared your clock objects as member variables of an SC_THREAD, which is a bad idea - when the thread ends, the clocks disappear. Also your thread has no infinite loop, so it will end immediately. The clock objects should be class members, something like this: //CLOCK DUT //clk_dut.h #include "systemc.h" SC_MODULE(clk_dut) { sc_clock refclk; sc_clock clk1; sc_clock clk2; SC_CTOR(clk_dut): refclk("refclk",100,SC_NS), clk1("clk1",10,SC_NS), clk2("clk2",5,SC_NS) { } }; If you want to declare them in a module, as you've shown, then you'll probably want to bind the clocks to some ports as well, regards Alan

David's post above should help http://forums.accellera.org/topic/1713-problem-while-trying-to-build-systemclib/?p=6501 regards Alan P.S. If you're on Linux, the you can get help on the patch command using man patch

Assertions count as functional coverage (at least according to section 16.2 of 1800-2012). You can disable all assertions with $assertoff. Otherwise "it's probably a tool issue". I don't have any other ideas re your question 2. regards Alan

For a functional untimed model, I guess the user needs to know how to set up and control the model, and how to integrate it into the rest of the system, and how to run it. It's not clear to me if this is an untimed model of the whole system. If it's for spec development and demo, I would expect it to output data for use as a reference later on, and perhaps to display that data in a useful form for a demo. Another way to think about it would be to develop "use cases" and then write the documentation according to that. So your person working on the design spec might say "I want to run the model and see a graph of the results" or "I want to run the model" "I need to set bus precision of data" "I need to output data as a video frame for import into Matlab" From those use cases, you should be able to derive the documentation. For the architect, I would expect to need to specify a register map and how to program the registers as well as the above. It's a very general question, so it's hard to answer! But thinking about use cases is probably a good place to start. kind regards Alan

I suggest that the key is to decide who you're writing the document for. If your model is going to be used for architectural analysis, then you should write the document for an architect. The next question, is what is the architect going to do? If they need to decide how to partition an algorithm between hardware and software then you have to assume that they need a model that can support both hardware and software. If you are targeting a known platform (e.g. a particular processor and bus and set of peripherals) then you can assume the CPU is fixed, and concentrate on the platform. In that case the architect needs to know how to configure the model to vary bus widths, bandwidth, bridges, and so on; and how to read performance information from the model. regards Alan

And the clock in your dff model should be declared sc_in<boo> clk; Alan

It would help to post the error message. However the error that stands out is q in your dff should be an output (sc_out<bool>), not an input, The wait() in tb_input waits until the rising edge of clk, which is every 10 ns. I'm not sure what you're asking about hierarchy. Have you seen this tutorial? http://www.doulos.com/knowhow/systemc/tutorial/ regards Alan