Jump to content
Sign in to follow this  
Adam Sherilog

UVM SystemVerilog Register Layer Basics Video Series

Recommended Posts

One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer.


The new video series is broken up into twelve clips:

  1. Introduction
  2. Testbench Integration
  3. Adapter
  4. Predictor & Auto Predict
  5. Register Model & Generation
  6. IP-XACT
  7. Register Model Classes
  8. Register API & Sequences
  9. Access Policies
  10. Frontdoor & Backdoor
  11. Predefined Sequences
  12. Demonstration

You are now registered for success!  (sorry, bad pun.  :) )


=Adam Sherilog, Cadence


Share this post

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this