Issue with single line comment in UVM Macro files

[mpeer]

Hi All,

I am using VCS Version F-2011.12.

While compiling uvm-1.1c package, I am getting compilation in some of the macro files.

Error comes in next line where single line comment is present (in between the definition of `define)

E.g.

File: $UVM_PKG_PATH/uvm-1.1c/src/macros/uvm_object_defines.svh

1. `define uvm_field_utils_end \

2. if(what__ inside {UVM_SETINT,UVM_SETSTR,UVM_SETOBJ}) begin \

3. // remove all scopes recorded (through super and other objects visited before) \

4. void'(__current_scopes.pop_back()); \

5. __m_uvm_status_container.m_uvm_cycle_scopes = __current_scopes; \

6. end \

7. end \

8. endfunction

Because of single line comment at line 3 (mentioned in above code), Error comes in line 4.

I changed all such comment in required files with multi-line comment and addtional space before backslash.

Line 3 after change:

3. /* remove all scopes recorded (through super and other objects visited before) */ \

Compilation is through with this change. Please let me know if there is any other option to get rid of such issues.

Thanks and Regards

Peer Mohammed

[petermonsson]

Hi Peer Mohammed ,

I don't remember which version that I have, but I don't remember having this problem. Do you have the latest release/patches from your vendor? I think that the single line comment is legal per the SystemVerilog LRM.

Best Regards

Peter

[mpeer]

Hi Peter,

I am using VCS Version F-2011.12.

I downloaded UVM package from Accelara site: UVM version uvm-1.1c.

When I compile this package using VCS tool. I get such error.

Regards

Peer Mohammed

[ajeetha.cvc]

You may want to look at $VCS_HOME/etc/* dir for built-in UVM and see if this was indeed necessary for VCS. Other option is to ask vcs_support@synopsys.com

Ajeetha, CVC

www.cvcblr.com/blog