UVM Testbench Architecture for Beginner

[hbeck]

Hi,

I'm pretty new in the world of UVM and need a hint for my first testbench architecture. Thats what I have at the moment:

1. C++ Model that generates Stimuli data + DPI-Interface (SV)

2. DUT (VHDL)

3. C++ Model that generates Compare data for DUT output + DPI-Interface (SV)

At first I want to realize only the way of stimuli generation and processing to the DUT. The stimuli generator creates multiple data sets (about 50k bytes each) that need to be feed into the DUT in 32bit partitions. My first Idea was to set up a Consumer/Producer as shown here:

C++ / DPI =byte=> Producer =byte=> TLM Fifo =byte=> Consumer =32bit=> Interface =32bit=> DUT

Somehow its pretty hard for my as a beginner to map this setup to the general UVM structure (sequence item, sequence, sequencer, driver, ...).

Is my producer a sequencer or just producing sequence items?

Does my TLM fifo contain sequence items?

Is my consumer a driver? (in this case my fifo should hold sequences)

Or are all these questions nonsense?

Thanks for any help!