Alan is right. You are trying to compile the text file. This example works great for VCS with your given input:
module tb;
logic [15:0] mem [0:5];
initial begin
$readmemb("mem.dat", mem);
foreach(mem[i])
$display("mem[%0d]= b%b = d%d", i, mem[i], mem[i]);
end
endmodule
vlogan +v2k -sverilog tb.sv
vcs -R tb
mem[0]= b1000000000011010 = d32794
mem[1]= b0000000000011010 = d 26
mem[2]= b1000000000011010 = d32794
mem[3]= b1000000000011010 = d32794
mem[4]= b1000000000011010 = d32794
mem[5]= b0000000000011010 = d 26