Terry Posted October 19, 2012 Report Share Posted October 19, 2012 Hi, I define the write task which combined to the uvm_analysis_imp, but when ncsim, it assert the warning as below: ncelab: *W,NOTVFW (/auto/tools/uvm/uvm-1.1/src/tlm1/uvm_analysis_port.svh,114|14): Expecting a SystemVerilog void function name. The task 'write' should be made a void function, not a task. Currently this is treated as a warning for backward compatibility but be aware that calling a task in this context is illegal SystemVerilog and can give unpredictable results. Further, this condition may be treated as an error in the future. sometimes we want to emit a action when writting a tlm into one component, and some delay action might be happened, so I think the task implemention will be better. why we use the function void type. Can anybody help me to slove this confusion. Thanks terry Quote Link to comment Share on other sites More sharing options...
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