why use the "function void" implemention about the write_* task of uvm_analysis_imp

[Terry]

Hi,

I define the write task which combined to the uvm_analysis_imp, but when ncsim, it assert the warning as below:

ncelab: *W,NOTVFW (/auto/tools/uvm/uvm-1.1/src/tlm1/uvm_analysis_port.svh,114|14): Expecting a SystemVerilog void function name. The task 'write' should be made a void function, not a task. Currently this is treated as a warning for backward compatibility but be aware that calling a task in this context is illegal SystemVerilog and can give unpredictable results. Further, this condition may be treated as an error in the future.

sometimes we want to emit a action when writting a tlm into one component, and some delay action might be happened, so I think the task implemention will be better. why we use the function void type.

Can anybody help me to slove this confusion.

Thanks

terry

[uwes]

hi,

an analysis-imp ends up in a write() function! because the "function" is a strong guarantee that it will never take time. the analysis-tlm connection is guaranteed to complete in zero time. it sounds like an "analysis" tlm connection is not what you want.

/uwe

[Terry]

Hi uwes,

Thanks for your reply!

I still confused why analysis_imp ends up in a write function but not task, for port connection, the put operation will not consume time both. if analysis_imp ends up in a task body, we can deal with this tlm by calling some task. but ends up in fucntion, we can not call the task directly and need to store it first.

Thanks

terry

[uwes]

hi,

if a analysis_imp would end in a "task" it could not be statically determined if this connection adheres to the contract of an analysis connection (which is zero time). this is because the task COULD take time violating the TLM contract. you can fork/join_none something within the function if this is required but the write() needs to return instantly.

/uwe