Adam Sherilog Posted October 10, 2012 Report Share Posted October 10, 2012 Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple language in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Cadence saw this need in the years leading to the UVM and was the first to contribute a multi-language solution. This solution was updated several times during the past four years to remain synchronized with UVM and add new functionality. On Thursday October 25 at 9a PDT we'll review the solution and discuss new features. Join us through this link: http://www.cadence.com/cadence/events/Pages/eventseries.aspx?series=Functional%20Verification%20Webinar%20Series%202012&CMP=Home =Adam Sherer, Cadence Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.