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Unit Level Vs Top level Scoreboard : Fundamental Question

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I had a fundamental question regarding how the flow for Scoreboarding(SB) really should be.

Let say we have SB at unit level for all the sub-module in the design, how should we go about stitiching these at top:

Option A : Tap the internal signals(each sub-module boundary signals) provide it to all the module level SB, while doing the top level run.

Option B : Create a new Top level SB which sees only Top level signals. You can take help of the module level SB wherever possible but, you are not allowed to tap those internal signals

Option A give us advantage of Reuse, finding/localizing issues at boundary level. But we can use this for Gate Level sims

Option B gives us advantage of using the SB for gate level sims... but involves a lot of rework.

One of the accellera Power Points suggests Option B and further suggests to disable the SB during Gate Level sims.

Que: If the SB is disabled at Gate Level Sim, what do we acheive with them.

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My suggestion is to use option A and B the following way:

1) Identify all conversions from X to Y in your scoreboards. Almost all scoreboards will do some type of conversion.

2) Factor out all conversions from X to Y into their own components (for example a predictor)

3) For the block level test bench take the simple predictors and connect them with a comparator to form a block level scoreboard

4) For the chip level test bench chain the appropriate components and match them up with a comparator

This is of course easier said than done.

I hope this helps


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