Simulation does not enter Body of the sequence.

[just4uvm]

I have all the components defined. But for some reason, simulation does not enter the 'body' of the sequence that I expected to execute. I have some messages I'm trying to display inside the body, pre_body and post_body but none of these are printed. Can anyone point me to what I'm doing wrong?

Thanks

[uwes]

pretty hard to tell without more info but its good to validate things step by step

1. all components instantiated

2. all components build

3. invoking .super() in all _phase() fiunctions/tasks

4. running in active mode (so sequencers are built)

5. right sequence configured?

6. is the right sequence selected? (check the messages talking about default-sequence)

7. starting the sequence manually? is the code started

8. which phase is used for the sequence?

9 is the phase protected from ending using objections?

10. is the expected printout in a function/task which really gets executed (pre_body is only executed for root sequences)

11...

/uwe

[just4uvm]

Thanks uwe for the detailed response. I created this UVC based on one that was in PASSIVE mode. And I forgot to change this to ACTIVE mode. Once I changed the mode, it works fine.