predefined register sequences usage

[raghavendrap]

Hello all,

I have generated register model and hooked up to my environment.

After that i am trying to run the predefined register reset sequence.

I am seeing below warnings,

UVM_WARNING /tools/synopsys/2011.03/vcsmx_sp1/etc/uvm/src/reg/uvm_reg_map.svh(1212) @ 0: reporter [RegModel] map 'uvm_reg_map' does not seem to be initialized correctly, check that the top register model is locked()

UVM_WARNING /tools/synopsys/2011.03/vcsmx_sp1/etc/uvm/src/reg/uvm_reg_map.svh(1212) @ 0: reporter [RegModel] map 'uvm_reg_map' does not seem to be initialized correctly, check that the top register model is locked()

Can anyone help me out how to overcome those warnings?

Thank you

Raghavendra

[adielkhan]

Probably you didn't use ralgen -uvm to generate SV uvm register code.

Once you do that you need to lock() the model in the user code.

Please also see post http://www.uvmworld.org/forums/showthread.php?658-Locking-register-blocks-and-building-system-level-register-blocks.

thanks

adiel

[lisakb1963]

Prior to calling the reset sequence, you need to pass the model to it:

If it is in a phase call:

virtual task run_phase(uvm_phase phase)
    phase.raise_object(this,"Running HW reset seq...");
   uvm_reg_hw_reset_test = new("test_seq");   // you really should use create to put it in the database
   test_seq.model = your_reg_model_name;
   test_seq.start(null);
   phase.drop_objection(this, "End of HW Reset seq...");
endtask