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[uvm_reg] why A0,A1 and RU VMM RAL types are disappeared in uvm_reg?

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Hi UVM exports,

We are recently migrating some register tests from VMM to UVM and find UVM adds many new kinds of registers compared with VMM. however, why there are 3 types of registers A0, A1 and RU have been removed?

Is it because reigster model does not actually care DUT updates the register value during operation.


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