Control verification components from sequence

[mwhite_cp]

I would like to have a way to control verification components from sequence. For example, I don't want to enable monitor check until initial configuration sequence is done. How can I accomplish this?

[phuynh]

One way to do this is to add an analysis port to your sequencer. Your sequence can now broadcast an event through the analysis port using:

p_sequencer.<analysis_port_name>.write(<whatever>);

Components that need to detect this event can subscribe to this analysis port.

Edited June 25, 2012 by phuynh

[mwhite_cp]

One way to do this is to add an analysis port to your sequencer. Your sequence can now broadcast an event through the analysis port using:

p_sequencer.<analysis_port_name>.write(<whatever>);

Components that need to detect this event can subscribe to this analysis port.

Thank you, I didn't know you can do this.

[yeewang]

One way to do this is to add an analysis port to your sequencer. Your sequence can now broadcast an event through the analysis port using:

p_sequencer.<analysis_port_name>.write(<whatever>);

Components that need to detect this event can subscribe to this analysis port.

You said "one way to do this". Is there any other ways?

[yeewang]

Is it possible/good to use resource db to pass information from sequencer to scoreboard for such purpose?

[mwhite_cp]

Yes, I believe you can. Someone recommended using uvm_config_db to enable/disable components during run time. I have not tried neither method yet.

[itsmyturn]

You said "one way to do this". Is there any other ways?

I think your monitor checking code itself can be made conditional based on a configuration variable in your agent cfg object. You can disable the monitor checking by default, and then when your initialization/configuration sequence is done, your sequence can get the env/agent cfg object and enable the checking.