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Getting blank output when running the program, Am i using topmodule correctly?


fayz

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#include <systemc.h>
#include "fetchunit.h"

SC_MODULE(DECODE_R) {
    sc_out<sc_int<7>> opcode;
    sc_out<sc_int<5>> rd,rs1,rs2;
    sc_out<sc_int<3>> func3;
    sc_out<sc_int<7>> func7;
    sc_in < sc_int<32>> writedata;
    sc_in_clk clk;
    

    SC_CTOR(DECODE_R)  {
        SC_THREAD(rtype);
        sensitive << clk.pos() ;

        
    }
    
    void rtype() {
        while (true) {
            wait(clk.posedge_event());
            
            cout << writedata.read().range(6, 0).to_int() << endl;

            if (writedata.read().range(6, 0) == 51 && writedata.read().range(14, 12) == 0 && writedata.read().range(31, 25) == 0) {
                cout << "R-TYPE ADD INSTRUCTION" << endl;
                opcode.write(writedata.read().range(6, 0));
                rd.write(writedata.read().range(11, 7));
                func3.write(writedata.read().range(14, 12));
                rs1.write(writedata.read().range(19, 15));
                rs2.write(writedata.read().range(24, 20));
                func7.write(writedata.read().range(31, 25));


            }
            else {
                cout << "code running" << endl;
            }
        }
    }

};
SC_MODULE(TopLevelModule) {
    FETCH fetch_inst;
    DECODE_R decode_r_inst;

    
    sc_signal<sc_int<32>> writedata_signal;
    sc_signal<sc_int<5>> rd, rs1, rs2;
    sc_signal<sc_int<3>> func3;
    sc_signal<sc_int<7>> func7, opcode;

    sc_signal<bool> clk;
    

    SC_CTOR(TopLevelModule) : fetch_inst("FetchInstance"), decode_r_inst("DecodeRinstance") {

        
        fetch_inst.writedata(writedata_signal);
        fetch_inst.clk(clk);

        decode_r_inst.opcode(opcode);
        decode_r_inst.rd(rd);
        decode_r_inst.rs1(rs1);
        decode_r_inst.rs2(rs2);
        decode_r_inst.func3(func3);
        decode_r_inst.func7(func7);
        decode_r_inst.writedata(writedata_signal);
        decode_r_inst.clk(clk);


        
    }

};


int sc_main(int argc, char* argv[]) {
    sc_set_time_resolution(1, SC_SEC);
    sc_clock clk("clk", 2, SC_SEC);
    sc_signal<sc_int<32>> writedata_signal;
    

    
    TopLevelModule TOPMODULE("TOP");
    

    sc_trace_file* tf = sc_create_vcd_trace_file("decode");
    sc_trace(tf, TOPMODULE.decode_r_inst.clk, "clk");
    sc_trace(tf, TOPMODULE.decode_r_inst.writedata, "writedata");
    sc_trace(tf, TOPMODULE.decode_r_inst.opcode, "opcode");
    sc_trace(tf, TOPMODULE.decode_r_inst.rd, "rd");
    sc_trace(tf, TOPMODULE.decode_r_inst.rs1, "rs1");
    sc_trace(tf, TOPMODULE.decode_r_inst.rs2, "rs2");
    sc_trace(tf, TOPMODULE.decode_r_inst.func3, "func3");
    sc_trace(tf, TOPMODULE.decode_r_inst.func7, "func7");
    sc_trace(tf, TOPMODULE.fetch_inst.pc_value, "pc");

    sc_start(5, SC_SEC);

    sc_close_vcd_trace_file(tf);
    

    return 0;
}

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There is no connection between the sc_clock "generator" declared in sc_main and the sc_signal 'clk' in TopLevelModule. This means the 'clk' signal connected to your decode instance is not toggling.

You have two options:

  • Move the sc_clock generator inside the TopLevelModule, to replace the floating sc_signal.
  • Change the TopLevelModule to take the clock as an input (sc_in_clk clk), and in sc_main connect the sc_clock generator 'clk' to the input port: TOPMODULE.clk(clk)

 

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Thanks, second approach worked for me.

8 hours ago, Matt Bone said:

There is no connection between the sc_clock "generator" declared in sc_main and the sc_signal 'clk' in TopLevelModule. This means the 'clk' signal connected to your decode instance is not toggling.

You have two options:

  • Move the sc_clock generator inside the TopLevelModule, to replace the floating sc_signal.
  • Change the TopLevelModule to take the clock as an input (sc_in_clk clk), and in sc_main connect the sc_clock generator 'clk' to the input port: TOPMODULE.clk(clk)

 

me.

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