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Is it possible to use `defines in IPXACT


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I have a use case where in i wanted to define the range of memory to be macro dependent.

so that i dont have to evaluate the XML file again and again.

For example ,







So with this macros i need not rerun the XML for changing the field Range.

is it possible to use `defines in IPXACT. Or any alternative solutions.

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@PrashanthP are you describing your design hierarchically in IP-XACT, or just generating leaf-level RTL?

I'm not sure what you mean by needing to re-generate your SV code, unless your tooling doesn't support generating parameterized RTL. It'll depend on the vendor, but if you declare a moduleParameter in your component/componentInstantiation, that can be used by RTL generators to create parameterized RTL modules from the IP-XACT. Something like this:


  <!-- ... -->
    <parameter parameterId="RANGE_PARAM" resolve="user">

At least, that's one way I've seen it done. I really have no idea what number of RTL generators actually create parameterized RTL.

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Hi Jason.

We are using xml file to generate register model from testbench standpoint.

my usecase is to define the depth of the memory parameterizable. When the paramter values are contolled from Testbench and not from the parameter field called "value".

If it is controlled from "value" field, every time i change the paramter value, i have to rerun the xml file for generating system verilog files(.sv files) which i don't need.

When we run xml file which has memory configuration, it will create below class definition 

class my_mem extends uvm_mem;


function new (input string name ="mem_class");

super.new(name,<field Range>,<field width>,<access _policy>,coverage); // super.new(name,'h40,8,"RW",coverage);

//i wanted is -> super.new(name,paramter_name*'h10,8,"RW",coverage); where paramter_name is controlled from TB



I just wanted to control the field "Width" from testbench. If i can then i need not run xml file again to generate memory with other depth. I will simply control it from TB.

If there is a possiblity please let me know.

Thanks and Regards,


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Got it, yes, your UVM RAL generator also needs to support parameterization. From what you are showing, the generator you are using doesn't support generating "parameterized" models. Again, I don't know how many, if any, of the big vendor companies support that, but it's certainly doable if you own the generator. You can use parameterized classes, though that is not required. You can also add instance attributes to the uvm_* classes which hold parameter values. The implementation is beyond the scope of this forum, but I have seen RAL models generated from IP-XACT which have "configurable" classes to align with the parametrizable register module RTL.

IP-XACT can capture the parameterization information, but your UVM RAL generator needs to support creation of configurable classes.

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