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jhpark

Simulation blocked at waiting statement in main_phase

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Dear,

I am implementing UVM code for reset test using reset_phase and main_phase with Cadence IES.

My test sequence injects multiple resets during simulation.

Main_phase in agent1 waits for event "posedge top.resetn" and another main_phase in agent2 waits for event "negedge top.resetn".

But two main_phase do not proceed, they are blocked at waiting statement.

What's the problem?

Thanks & Regards,

//JunH Park

P.S. I attached three contents.

1. my code : test.sv

2. run script

3. irun.log file

1. test.sv

--------------------------------------------------------------------------------------------

import uvm_pkg::*;

`include "uvm_macros.svh"

// ------------------------------------------

//

// Agent

//

// ------------------------------------------

class simple_agent1 extends uvm_agent;

int agent_cnt;

`uvm_component_utils(simple_agent1)

function new (string name, uvm_component parent);

super.new(name, parent);

endfunction : new

extern virtual function void build_phase(uvm_phase phase);

extern virtual task reset_phase(uvm_phase phase);

extern virtual task main_phase(uvm_phase phase);

endclass : simple_agent1

function void simple_agent1::build_phase(uvm_phase phase);

super.build();

endfunction

task simple_agent1::reset_phase(uvm_phase phase);

`uvm_info(get_type_name(), $sformatf("-----> reset_phase"), UVM_LOW)

agent_cnt = 1000;

endtask

task simple_agent1::main_phase(uvm_phase phase);

`uvm_info(get_type_name(), $sformatf("main_phase ----->"), UVM_LOW)

@(posedge top.resetn);

`uvm_info(get_type_name(), $sformatf("----- after posedge top.reset"), UVM_LOW)

forever begin

agent_cnt++;

`uvm_info(get_type_name(), $sformatf("main_phase[%0d]", agent_cnt), UVM_LOW)

#10;

end

`uvm_info(get_type_name(), $sformatf("-----> main_phase"), UVM_LOW)

endtask

// ------------------------------------------

//

// Agent2

//

// ------------------------------------------

class simple_agent2 extends uvm_agent;

bit once = 1;

`uvm_component_utils(simple_agent2)

function new (string name, uvm_component parent);

super.new(name, parent);

endfunction : new

extern virtual task reset_phase(uvm_phase phase);

extern virtual task main_phase(uvm_phase phase);

endclass : simple_agent2

task simple_agent2::reset_phase(uvm_phase phase);

`uvm_info(get_type_name(), $sformatf("-----> reset_phase"), UVM_LOW)

endtask

task simple_agent2::main_phase(uvm_phase phase);

`uvm_info(get_type_name(), $sformatf("main_phase ----->"), UVM_LOW)

@(negedge top.resetn);

`uvm_info(get_type_name(), "", UVM_LOW)

`uvm_info(get_type_name(), "", UVM_LOW)

`uvm_info(get_type_name(), "--------------- RESET ---------------", UVM_LOW)

`uvm_info(get_type_name(), "", UVM_LOW)

`uvm_info(get_type_name(), "", UVM_LOW)

`uvm_info(get_type_name(), $sformatf("-----> main_phase"), UVM_LOW)

endtask

// ------------------------------------------

//

// vseqr

//

// ------------------------------------------

class vseqr_c extends uvm_sequencer;

`uvm_component_utils(vseqr_c)

function new (string name, uvm_component parent);

super.new(name, parent);

endfunction : new

endclass : vseqr_c

// ------------------------------------------

//

// TB

//

// ------------------------------------------

class tb_c extends uvm_env;

`uvm_component_utils(tb_c)

vseqr_c vseqr;

simple_agent1 agent;

simple_agent2 agent2;

function new (string name, uvm_component parent);

super.new(name, parent);

endfunction : new

function void build_phase(uvm_phase phase);

super.build();

vseqr = vseqr_c::type_id::create("vseqr", this);

agent = simple_agent1::type_id::create("agent", this);

agent2 = simple_agent2::type_id::create("agent2", this);

endfunction

endclass : tb_c

// ----------------------------------------

//

// Test case

//

// ----------------------------------------

class simple_test extends uvm_test;

bit once = 1;

tb_c tb;

int test_cnt;

`uvm_component_utils(simple_test)

function new(string name, uvm_component parent);

super.new(name, parent);

endfunction : new

function void build_phase(uvm_phase phase);

super.build();

tb = tb_c::type_id::create("tb", this);

uvm_config_db#(uvm_object_wrapper)::set(this, "tb.vseqr.run_phase", "default_sequence", simple_vseq_c::type_id::get());

endfunction

endclass : simple_test

// ------------------------------------------

//

// Verilog top module

//

// ------------------------------------------

module top;

reg resetn;

initial begin

run_test("simple_test");

end

initial begin

$shm_open("test.shm");

$shm_probe("AS");

end

endmodule

// ------------------------------------------

//

// TEST sequence - virtual sequence

//

// ------------------------------------------

class simple_vseq_c extends uvm_sequence;

`uvm_object_utils_begin(simple_vseq_c)

`uvm_object_utils_end

`uvm_declare_p_sequencer(vseqr_c)

function new (string name = "simple_vseq_c");

super.new(name);

endfunction : new

virtual task pre_body();

if (starting_phase != null) begin

`uvm_info(get_type_name(), "objection is raised", UVM_LOW)

starting_phase.raise_objection(this, {"Run sequence '", get_full_name(), "'"});

end

endtask

virtual task body();

`uvm_info(get_type_name(), "Start of body() in vseq", UVM_LOW)

top.resetn = 1;

`uvm_info(get_type_name(), "RESET = 1", UVM_LOW)

// --- 1st RESET

#50

top.resetn = 0;

`uvm_info(get_type_name(), "RESET = 0", UVM_LOW)

#50

top.resetn = 1;

`uvm_info(get_type_name(), "RESET = 1", UVM_LOW)

// --- Operation

#300

// --- 2nd RESET

#50

top.resetn = 0;

`uvm_info(get_type_name(), "RESET = 0", UVM_LOW)

#50

top.resetn = 1;

`uvm_info(get_type_name(), "RESET = 1", UVM_LOW)

// --- Operation

#400

`uvm_info(get_type_name(), "End of body() in vseq", UVM_LOW)

endtask

virtual task post_body();

if (starting_phase != null) begin

`uvm_info(get_type_name(), "objection is dropped", UVM_LOW)

starting_phase.drop_objection(this, {"Run sequence '", get_full_name(), "'"});

end

endtask

endclass : simple_vseq_c

// ------------------------------------------

//

// Define report format

//

// ------------------------------------------

class report_server_c extends uvm_report_server;

static bit initialized = init();

static function bit init();

uvm_report_global_server global_report_server = new;

report_server_c mysrv = new;

global_report_server.set_server(mysrv);

endfunction: init

virtual function string compose_message(uvm_severity severity,

string name,

string id,

string message,

string filename,

int line);

string msg = "";

uvm_severity_type sv;

sv = uvm_severity_type'(severity);

$timeformat(-9, 0, "", 20);

$sformat(msg, "[%0t] %0s (%0s) %0s", $time, sv.name, id, message);

return msg;

endfunction: compose_message

endclass: report_server_c

--------------------------------------------------------------------------------------------------------------

2. run_script

--------------------------------------------------------------------------------------------

#!/bin/csh -f

irun \

test.sv \

-uvmhome /appl/SOL/INCISIV/INCISIV102s029/tools/uvm-1.1 \

+UVM_TIMEOUT=1000000 \

-timescale 1ns/10ps \

+UVM_VERBOSITY=UVM_LOW \

-access +rwc

--------------------------------------------------------------------------------------------

3. irun.log file

--------------------------------------------------------------------------------------------

irun: 10.21-s010: © Copyright 1995-2012 Cadence Design Systems, Inc.

TOOL: irun 10.21-s010: Started on May 17, 2012 at 08:45:13 KST

irun

test.sv

-uvmhome /appl/SOL/INCISIV/INCISIV102s029/tools/uvm-1.1

+UVM_TIMEOUT=1000000

-timescale 1ns/10ps

+UVM_VERBOSITY=UVM_LOW

-access +rwc

...

[0] UVM_INFO (RNTST) Running test simple_test...

[0] UVM_INFO (TIMOUTSET) '+UVM_TIMEOUT=1000000' provided on the command line is being applied.

[0] UVM_INFO (simple_vseq_c) objection is raised

[0] UVM_INFO (simple_vseq_c) Start of body() in vseq

[0] UVM_INFO (simple_vseq_c) RESET = 1

[0] UVM_INFO (simple_agent2) -----> reset_phase

[0] UVM_INFO (simple_agent1) -----> reset_phase

[0] UVM_INFO (simple_agent2) main_phase ----->

[0] UVM_INFO (simple_agent1) main_phase ----->

[50] UVM_INFO (simple_vseq_c) RESET = 0

[100] UVM_INFO (simple_vseq_c) RESET = 1

[450] UVM_INFO (simple_vseq_c) RESET = 0

[500] UVM_INFO (simple_vseq_c) RESET = 1

[900] UVM_INFO (simple_vseq_c) End of body() in vseq

[900] UVM_INFO (simple_vseq_c) objection is dropped

[900] UVM_INFO (TEST_DONE) 'run' phase is ready to proceed to the 'extract' phase

--- UVM Report catcher Summary ---

Number of demoted UVM_FATAL reports : 0

Number of demoted UVM_ERROR reports : 0

Number of demoted UVM_WARNING reports: 0

Number of caught UVM_FATAL reports : 0

Number of caught UVM_ERROR reports : 0

Number of caught UVM_WARNING reports : 0

--- UVM Report Summary ---

** Report counts by severity

UVM_INFO : 16

UVM_WARNING : 0

UVM_ERROR : 0

UVM_FATAL : 0

** Report counts by id

[RNTST] 1

[TEST_DONE] 1

[TIMOUTSET] 1

[simple_agent1] 2

[simple_agent2] 2

[simple_vseq_c] 9

Simulation complete via $finish(1) at time 900 NS + 46

/appl/SOL/INCISIV/INCISIV102s029/tools/uvm-1.1/uvm_lib/uvm_sv/sv/base/uvm_root.svh:408 $finish;

ncsim> exit

TOOL: irun 10.21-s010: Exiting on May 17, 2012 at 08:45:21 KST (total: 00:00:08)

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