Trying to assign a sc_bv to a combined variable vector (x,y,z) of same width

[Llama]

Hi , I have some variable bit-length variables like, 

sc_uint<10> x;

sc_bit y;

sc_int<8> z;

and a bit vector sc_bv<19> a;

Note: Combined bit-length of x,y,z is equal to length of a.

I'm able to assign the combined vector to the bit_vector a like, a = (x,y,z);

However I'm unable to do the reverse assignment like, (x,y,z) = a;

Please provide suggestions to achieve the above.

 

[David Black]

6 minutes ago, Llama said:

Hi , I have some variable bit-length variables like, 

sc_uint<10> x;

sc_bit y;

sc_int<8> z;

and a bit vector sc_bv<19> a;

Note: Combined bit-length of x,y,z is equal to length of a.

I'm able to assign the combined vector to the bit_vector a like, a = (x,y,z);

However I'm unable to do the reverse assignment like, (x,y,z) = a;

Please provide suggestions to achieve the above.

 

SystemC is C++. SystemC is neither Verilog nor VHDL. 

You could create a simple class with a constructor to take apart a vector. With some clever trickery you might even be able to coax a C++11 variadic template to do exactly what you want.