acc_sysC Posted March 3, 2023 Report Posted March 3, 2023 Below is a snippet of the stimulus I am giving to my design. I want all of the assignments to be non-blocking and so I have declared everything as sc_signal. However, the problem arises with the need to use range() Here ACC, B and Y use range(). Since range() cannot be used with sc_signal, I used a copy of them as a sc_bv. I think because of this, the statements are becoming blocking assignments in between and these signals are always 0 in my waveform. Please suggest ways to deal with this problem. sc_signal<sc_bv<M> >A; sc_signal<sc_bv<M> >B; sc_signal<sc_bv<1<<M> > FUNC; constexpr static int size = ceil(log2(M)); sc_signal<sc_uint<size> > FUNC_ADDR; sc_signal<sc_bv<N> > LOAD_CORE; constexpr static int size_addr = ceil(log2(2*(N-1))); sc_signal<sc_bv<N*size_addr> > AIN_ADDR; sc_signal<sc_bv<N*size_addr> > BIN_ADDR; sc_signal<sc_bv<2*N> > SRC_MODE; sc_signal<sc_bv<2*N> > IN_MODE; sc_signal<sc_bv<N> > RUN; //sc_clock clk("clock", 6, SC_NS); //sc_signal<bool> clk; sc_in_clk clk; sc_signal<bool> reset; constexpr static int size_y_addr = ceil(log2(N)); sc_signal<sc_bv<size_y_addr> > Y_ADDR; sc_signal<sc_bv<M> > Y; sc_signal <sc_bv<16> > Accumulator; sc_bv<M>Y_copy; sc_bv<16> ACC = 0; sc_bv<M> B_copy; * * * CODE * * * wait(clk.posedge_event());//1 A.write(36); B.write(129); IN_MODE.write(0x3FC00); SRC_MODE.write(0x3FC00); AIN_ADDR.write(0x223300000); BIN_ADDR.write(0x010100000); wait(clk.posedge_event());//2 //wait(6,SC_NS); B_copy = B.read(); B_copy.range(3,0) = ACC.range(3,0); B.write(B_copy); IN_MODE.write(0x00333); SRC_MODE.write(0x00001); AIN_ADDR.write(0x0B0C00); BIN_ADDR.write(0xD0F0E); RUN.write(0x1E0); wait(clk.posedge_event());//3 Y_copy = Y.read(); B_copy.range(3,0) = ACC.range(7,4); B.write(B_copy); IN_MODE.write(0x003BB); SRC_MODE.write(0x00113); AIN_ADDR.write(0x80800); BIN_ADDR.write(0x87A38); RUN.write(0x015); wait(clk.posedge_event());//4 B_copy.range(3,0) = ACC.range(11,8); B.write(B_copy); IN_MODE.write(0x00357); SRC_MODE.write(0x00201); AIN_ADDR.write(0x17638); BIN_ADDR.write(0x00002); RUN.write(0x015); Y_ADDR.write(0x0000); wait(clk.posedge_event());//5 Y_copy = Y.read(); ACC.range(7,4) = Y_copy.range(3,0); Accumulator.write(ACC); B_copy.range(3,0) = ACC.range(15,12); B.write(B_copy); IN_MODE.write(0x003E3); SRC_MODE.write(0x00342); AIN_ADDR.write(0x08006); BIN_ADDR.write(0x89208); RUN.write(0x01B); wait(clk.posedge_event());//6 IN_MODE.write(0x00333); SRC_MODE.write(0x00121); AIN_ADDR.write(0x80408); BIN_ADDR.write(0x10802); RUN.write(0x01D); wait(clk.posedge_event()); //7 ACC.range(11,8) = Y_copy.range(3,0); Accumulator.write(ACC); IN_MODE.write(0x0000B); SRC_MODE.write(0x00002); AIN_ADDR.write(0x00006); BIN_ADDR.write(0x00028); RUN.write(0x015); wait(clk.posedge_event());//8 IN_MODE.write(0x00004); SRC_MODE.write(0x00000); AIN_ADDR.write(0x00000); BIN_ADDR.write(0x00000); RUN.write(0x001); Y_ADDR.write(0x0001); wait(clk.posedge_event());//9 ACC.range(15,12) = Y_copy.range(3,0); Accumulator.write(ACC); IN_MODE.write(0x00000); RUN.write(0x002); wait(clk.posedge_event());//10 Y_ADDR.write(0x0000); IN_MODE.write(0x00000); RUN.write(0x000); Quote
Eyck Posted March 3, 2023 Report Posted March 3, 2023 SystemC has no comcept of blocking or non-blocking assignments. If you write to a signal you write to the signal immediatly and the result becomes visible in the next delta cycle. So you parts like Y_copy = Y.read(); ACC.range(7,4) = Y_copy.range(3,0); Accumulator.write(ACC); are correct. You may shortern this to ACC.range(7,4) = Y.read().range(3,0); Accumulator.write(ACC); So you may have an issue in other parts of your code. Quote
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