Verify shared address map with stand-alone and unified enable signals by RGM or REG?

[leo_chen]

There are 3 channels in my DUT, these 3 channels have the same register files, which have the same address map.

There are 4 CE (channel enable signal) on the interface, CE0, CE1, CE2 and CE_all.

There is only one address signal and one write data signal, like normal bus.

When a write transaction is initiated ...

If CE_all is asserted, the selected registers in all 3 channels are written.

If only CE0 is asserted, only the selected register in channel 0 is written.

If only CE1 is asserted, only the selected register in channel 1 is written.

If only CE2 is asserted, only the selected register in channel 2 is written.

The same address on the bus, but may have 4 different effects.

I am not sure if I can implement the register files for this specification by Cadence's RGM or UVM_REG?

The most challenging thing I can imagine so far is that CE_all need to update all register database.

Shared address map is also a problem, maybe using different register database can help, but contradict CE_all case.

Please kindly help.

Thanks.

Edited May 9, 2012 by leo_chen

[leo_chen]

My plan so far:

I will try to map different base addresses to these 4 CE's, and use mirroring feature of RGM.

Edited May 9, 2012 by leo_chen

[janick]

Who controls the CE_* signal? if that is the bus master, they can be treated as additional address bits. You'd have to extend the register model (via callbacks) to reflect accesses done in the "CE_all" space to the mirrored values of the other registers.

If these signals are externally controlled, you'd have to use a user-defined frontdoor to make sure the right CE_x signal is asserted to acess a particular instance of a register.

P.S. You are aware that "RGM" is *NOT* part of the UVM standard, aren't you??

[leo_chen]

Who controls the CE_* signal? if that is the bus master, they can be treated as additional address bits. You'd have to extend the register model (via callbacks) to reflect accesses done in the "CE_all" space to the mirrored values of the other registers.

CE_* are controlled by an address decoder outside the DUT, so it should be this case.

I think post_access() should be the callback I should utilize in RGM for this case.

I never use UVM_REG, so not sure what callbacks it support for this case. (However, I think aliased register in UVM_REG is similar to mirrored register in RGM)

P.S. You are aware that "RGM" is *NOT* part of the UVM standard, aren't you??

Yes, I know.

I have not migrated to UVM yet, but already had some OVM RGM experience.

If there is an easy and free way to generate register classes for UVM_REG, like XML->SV provided in RGM package, I will try to use UVM_REG.

Thank you Janick, I learned very much from your book.

[amitshere]

I am sure there are multiple tools by different vendors which help to generate UVM REG SV models from IPXACT...

ralgen which ships with VCS also would help you generate UVM REG models from IPXACt

[leo_chen]

Thank you amitshere, I will contact Cadence FAE to get the tool and try UVM_REG.

I can't use VCS.

[lisakb1963]

You should contact your Cadence AE and ask for iregGen -- we don't post it, and it's not in the release yet. This is the current standard protocol.

It takes in IP-XACT 1.5 XML and uses the IEEE 1685-2009 (I think that's the spec) for the schemas. From there you can create:

UVM_REG -- which I use

OVM_RGM

UVM_RGM

There are some difference in the vendor extensions in the README file. Even if you have other tools in place (a lot of people want to take a word document and generate IP-XACT with non-free tools -- you should still use iregGen -- it will create the vendor extensions for the outputted register model correctly.

Callback hooks are generated for every register.