leo_chen Posted May 8, 2012 Report Share Posted May 8, 2012 (edited) There are 3 channels in my DUT, these 3 channels have the same register files, which have the same address map. There are 4 CE (channel enable signal) on the interface, CE0, CE1, CE2 and CE_all. There is only one address signal and one write data signal, like normal bus. When a write transaction is initiated ... If CE_all is asserted, the selected registers in all 3 channels are written. If only CE0 is asserted, only the selected register in channel 0 is written. If only CE1 is asserted, only the selected register in channel 1 is written. If only CE2 is asserted, only the selected register in channel 2 is written. The same address on the bus, but may have 4 different effects. I am not sure if I can implement the register files for this specification by Cadence's RGM or UVM_REG? The most challenging thing I can imagine so far is that CE_all need to update all register database. Shared address map is also a problem, maybe using different register database can help, but contradict CE_all case. Please kindly help. Thanks. Edited May 9, 2012 by leo_chen Quote Link to comment Share on other sites More sharing options...
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