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  1. But I only instantiated only one flash_if called "flash_if0".I thought I can assign different interfaces to the same "flash_if0" of different flash_monitor? My intention: (not SV syntax, just concept) flash_monitor[0].flash_if0 = top_testbench.flash_if0; flash_monitor[1].flash_if[COLOR="red"]0[/COLOR] = top_testbench.flash_if1;Is this possible? Or I need to instantiate many flash_if in flash_bus_monitor. Then : flash_monitor[0].flash_if0 = top_testbench.flash_if0; flash_monitor[1].flash_if[COLOR="red"]1[/COLOR] = top_testbench.flash_if1; Anyway, I will try it out. Thanks, Pratta.
  2. Hi, I am creating the testbench that includes 2 flash memory, so I instance 2 flash_if in top testbench, but some signals I found second instance (flash_if1) seems not assigned well. I dump the waveform of flash_if0 and flash_if1, when receiving the flash reset command, the flash signals on both flash_if0 and flash_if1 are the same. The reset detection mechanism in flash_bus_monitor[0] works well, but the same detection in flash_bus_monitor[1] doesn't work.:confused: Please kindly help. top testbench: flash_if flash_if0 (); flash_if flash_if1 (); initial begin uvm_config_db#(virtual flash_if)::set(uvm_root::get(), "*flash_monitor[0]", "flash_if0", flash_if0); uvm_config_db#(virtual flash_if)::set(uvm_root::get(), "*flash_monitor[1]", "flash_if0", flash_if1); //this one looks not work run_test(); end UVM environment: flash_bus_monitor flash_monitor[2]; function void build_phase(uvm_phase phase); super.build_phase(phase); for (byte i=0; i<2; i++) flash_monitor[i] = flash_bus_monitor::type_id::create($sformatf("flash_monitor[%0d]",i) , this); endfunction : build_phase flash_bus_monitor: virtual flash_if flash_if0; function void build_phase(uvm_phase phase); if(!uvm_config_db#(virtual flash_if)::get(this, "", "flash_if0", flash_if0)) `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".flash_if0"}); //neither flash_monitor[0] nor flash_monitor[1] trigger this fatal endfunction: build_phase Thanks in advance.
  3. Well, I think I know why now. When I display_objections(), the drain time is not passed yet. Now it looks good.
  4. Hi, I think the normal result of display_objections() should be like this: The total objection count is 2 --------------------------------------------------------- Source Total Count Count Object --------------------------------------------------------- 0 2 uvm_top 0 2 uvm_test_top 0 2 my_env 0 2 my_sequencer 2 2 my_seq ---------------------------------------------------------And I do see this when everything is OK.But somehow display_objections() prints the following messages, there is 0 objection source, but total objection count is 1. May I know what this means? The total objection count is 1 --------------------------------------------------------- Source Total Count Count Object --------------------------------------------------------- 0 1 uvm_top --------------------------------------------------------- I use uvm 1.0p1 since my simulator is not new enough to run 1.1a or 1.1b. Thanks in advance.
  5. Thank you amitshere, I will contact Cadence FAE to get the tool and try UVM_REG. I can't use VCS.
  6. CE_* are controlled by an address decoder outside the DUT, so it should be this case. I think post_access() should be the callback I should utilize in RGM for this case. I never use UVM_REG, so not sure what callbacks it support for this case. (However, I think aliased register in UVM_REG is similar to mirrored register in RGM) Yes, I know. I have not migrated to UVM yet, but already had some OVM RGM experience. If there is an easy and free way to generate register classes for UVM_REG, like XML->SV provided in RGM package, I will try to use UVM_REG. Thank you Janick, I learned very much from your book.
  7. My plan so far: I will try to map different base addresses to these 4 CE's, and use mirroring feature of RGM.
  8. There are 3 channels in my DUT, these 3 channels have the same register files, which have the same address map. There are 4 CE (channel enable signal) on the interface, CE0, CE1, CE2 and CE_all. There is only one address signal and one write data signal, like normal bus. When a write transaction is initiated ... If CE_all is asserted, the selected registers in all 3 channels are written. If only CE0 is asserted, only the selected register in channel 0 is written. If only CE1 is asserted, only the selected register in channel 1 is written. If only CE2 is asserted, only the selected register in channel 2 is written. The same address on the bus, but may have 4 different effects. I am not sure if I can implement the register files for this specification by Cadence's RGM or UVM_REG? The most challenging thing I can imagine so far is that CE_all need to update all register database. Shared address map is also a problem, maybe using different register database can help, but contradict CE_all case. Please kindly help. Thanks.
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