Should SystemC model be exactly same as the RTL in terms of the architecture of each module?

[acc_sysC]

For example, should the model have same number of ports as the RTL?

or are we allowed to add additional ports in the model to make it work logically?

Thanks

[Eyck]

The answer is a clear: it depends. In general you are allowed to do whatever is beneficial. If your SC module is supposed to replace the RTL module it should pin compatible. If this is not the case you may add additional ports or leave unused ports ouf.

The same applies to the architecture. If the SC module should behave exactly the same you will end up with the same architecture. But then you have the same module in another language -  I doubt that this is a goal as you do not gain anything. Usually you want to have a similar behavior e.g. when doing cycle-approximate models. In this case the architecture might be enirely different although usually you end up with a similar structure. But since you abstract some details away you can implement the behavior much more efficient and thus gain simulation performance.

[acc_sysC]

Hi @Eyck, that makes sense. Thanks for the explanation!