Bit-level register functional coverage not getting hit using RAL

[akshay.raoy]

I am using UVM and RAL for functional coverage for register.

I generated regmodel file using ralgen on ral.ralf file using the below command

ralgen -uvm -t x regmodel Uvmral.ralf -c bF  for field coverage

This generates regmodel.sv file with covergroups showing bit_level_coverage and field_coverage groups.

When I compile and run my testcase, I see bit_coverage is 0% hit but my field_coverage is >0%(I mean I see coverage on field).

In my env I am doing set_coverage(UVM_CVR_ALL) but generated regmodel.sv contains specific UVM_CVR_FIELD_VALS and UVM_CVR_REG_BITS covergroups for each registers. Here I used UVM_CVR_ALL thinking that it should be applicable to all.

I tried set_coverage(UVM_CVR_REG_BITS) and generated regmodel with command ralgen -uvm -t x regmodel Uvmral.ralf -c b only for bit_coverage. Still coverage for bit field is not hitting(In waveform I see each register bit getting exercised).

I don’t know where I am doing wrong. Please help me to resolve this issue. Is there any settings/commands I specifically need to pass/set??

Also what is the switch or command_line_argument for getting covergroup for UVM_CVR_ALL. I mean;

e.g I use b: bit-level(UVM_CVR_REG_BITS),

F: field values(UVM_CVR_FIELD_VALS). Similarly is there any command to get UVM_CVR_ALL?

[janick]

That's weird. Do you also specify UVM_CVR_ALL to uvm_reg::build_coverage()??

The sampling for field values is based on the mirror content and manually triggered. So it is conceivable that you are setting the mirror values (via set() or randomize()), then sampling the field value coverage, but not actually performing any physical read or write and thus have no actual bit coverage.