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akshay.raoy

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  1. Want to set attribute NO_REG_TESTS for few Status resigters, so that when reset sequence will disable reading the register. I have made uvm_resource_db#(bit)::set({"REG::",regmodel.debug_status.get_full_name(),".*"},"NO_REG_TESTS",1,this); uvm_resource_db#(bit)::set({"REG::",regmodel.debug_status.get_full_name(),".*"},"NO_REG_HW_RESET_TEST",1,this); in environment but still i could see debug_status register being tested. Can anyone give me the solution how to set this attributes. -Akshay Rao
  2. I am using UVM and RAL for functional coverage for register. I generated regmodel file using ralgen on ral.ralf file using the below command ralgen -uvm -t x regmodel Uvmral.ralf -c bF  for field coverage This generates regmodel.sv file with covergroups showing bit_level_coverage and field_coverage groups. When I compile and run my testcase, I see bit_coverage is 0% hit but my field_coverage is >0%(I mean I see coverage on field). In my env I am doing set_coverage(UVM_CVR_ALL) but generated regmodel.sv contains specific UVM_CVR_FIELD_VALS and UVM_CVR_REG_BITS covergroups for each registers. Here I used UVM_CVR_ALL thinking that it should be applicable to all. I tried set_coverage(UVM_CVR_REG_BITS) and generated regmodel with command ralgen -uvm -t x regmodel Uvmral.ralf -c b only for bit_coverage. Still coverage for bit field is not hitting(In waveform I see each register bit getting exercised). I don’t know where I am doing wrong. Please help me to resolve this issue. Is there any settings/commands I specifically need to pass/set?? Also what is the switch or command_line_argument for getting covergroup for UVM_CVR_ALL. I mean; e.g I use b: bit-level(UVM_CVR_REG_BITS), F: field values(UVM_CVR_FIELD_VALS). Similarly is there any command to get UVM_CVR_ALL?
  3. i am just using uvm_reg_bit_bash_seq which is with UVM package. monitoring is not done in my defined sequence. this is how i am using it. uvm_reg_bit_bash_seq pie8_ral_seq = uvm_reg_bit_bash_seq::type_id::create("pie8_ral_seq",this) pie8_ral_seq.model = tbEnv.regmodel; pie8_ral_seq.start(null);
  4. Its a read/write bit, this is the first bit of bit bash. yes DUT is idle, and i am able to see writing value 1 to each bit twice in waveform.
  5. uvm_reg_bit_bash_seq always writes value 1, both the times and always keep the exp value to default value of the register. in this sequence bash_kth_bit task i tried just adding rg.set(val) after write is done. it started working fine. i am using uvm-1.0p1 version of UVM package. Does anyone face this issue in uvm-1.1 also? or is it fixed in new version?
  6. rajiv, solution is same as jeffs reply. dont modify the transaction once data is present.
  7. I am trying to create and RAL for AHB bus. My adapter is not able to read the data correctly. My env uses a synopsis AHB VIP.VIP is configured to 32bit address and data. Write is working with this adapter. Read is delayed by one clock cycle which is making read data from adapter as 0’s always. Here is the sim.log displays from adapter: @ 78400823500: reporter [RAL ADAPTER] reg2bus rw.DATA = 00, rw.ADDRESS = 20c @ 78400823500: reporter [RAL ADAPTER] reg2bus tr.DATA = 00, tr.ADDRESS = 20c @78400823500 address is on reg2bus @ 78412835500: reporter [RAL ADAPTER] bus2reg rw.DATA = 00, rw.ADDRESS = 20c @ 78412835500: reporter [RAL ADAPTER] bus2reg tr.DATA = 00, tr.ADDRESS = 20c In waveform @78409832500 we can see data on hrdata lines, but bus2reg displays shows timestamps @ 78412835500: by this timestamp data is zero on hrdata. Can anyone tell me What should be made to adapter so that it read data at correct timestamp. I have attached the snapshot of read transaction at @ 78400823500,@78409832500,@ 78412835500 Here is the adapter code which I have implemented. class reg_adapter extends uvm_reg_adapter; `uvm_object_utils(reg_adapter) function new (string name = "reg_adapter"); super.new(name); provides_responses = 1; endfunction : new virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); pcie_dw_vip_ahb_master_transaction tr; tr = pcie_dw_vip_ahb_master_transaction::type_id::create("tr"); tr.m_enXactType = (rw.kind == UVM_READ) ? pcie_dw_vip_ahb_master_transaction::READ : pcie_dw_vip_ahb_master_transaction::WRITE; tr.m_enXferSize = pcie_dw_vip_ahb_master_transaction::XFER_SIZE_32BIT; tr.m_bvAddress = rw.addr; tr.m_nNumBytes = 4; tr.m_bvvData = new[4]; tr.m_bvvData[0] = rw.data[7:0]; tr.m_bvvData[1] = rw.data[15:8]; tr.m_bvvData[2] = rw.data[23:16]; tr.m_bvvData[3] = rw.data[31:24]; `uvm_info("RAL ADAPTER",$sformatf("reg2bus rw.DATA = %2h, rw.ADDRESS = %2h",rw.data,rw.addr),UVM_LOW); `uvm_info("RAL ADAPTER",$sformatf("reg2bus tr.DATA = %2h, tr.ADDRESS = %2h",{tr.m_bvvData[0],tr.m_bvvData[1],tr.m_bvvData[2],tr.m_bvvData[3]},tr.m_bvAddress),UVM_LOW); return tr; endfunction virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); pcie_dw_vip_ahb_master_transaction tr; if(!$cast(tr,bus_item))begin `uvm_fatal("NOT_HOST_REG_TYPE","bus_item is not correct type"); end rw.kind = (tr.m_enXactType == pcie_dw_vip_ahb_master_transaction::READ) ? UVM_READ : UVM_WRITE; tr.m_enXferSize = pcie_dw_vip_ahb_master_transaction::XFER_SIZE_32BIT; rw.addr = tr.m_bvAddress; tr.m_nNumBytes = 4; tr.m_bvvData = new[4]; rw.data[7:0] = tr.m_bvvData[0]; rw.data[15:8] = tr.m_bvvData[1]; rw.data[23:16] = tr.m_bvvData[2]; rw.data[31:24] = tr.m_bvvData[3]; rw.status = UVM_IS_OK; `uvm_info("RAL ADAPTER",$sformatf("bus2reg rw.DATA = %2h, rw.ADDRESS = %2h",rw.data,rw.addr),UVM_LOW); `uvm_info("RAL ADAPTER",$sformatf("bus2reg tr.DATA = %2h, tr.ADDRESS = %2h",{tr.m_bvvData[0],tr.m_bvvData[1],tr.m_bvvData[2],tr.m_bvvData[3]},tr.m_bvAddress),UVM_LOW); endfunction endclass
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