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  1. Want to set attribute NO_REG_TESTS for few Status resigters, so that when reset sequence will disable reading the register. I have made uvm_resource_db#(bit)::set({"REG::",regmodel.debug_status.get_full_name(),".*"},"NO_REG_TESTS",1,this); uvm_resource_db#(bit)::set({"REG::",regmodel.debug_status.get_full_name(),".*"},"NO_REG_HW_RESET_TEST",1,this); in environment but still i could see debug_status register being tested. Can anyone give me the solution how to set this attributes. -Akshay Rao
  2. I am using UVM and RAL for functional coverage for register. I generated regmodel file using ralgen on ral.ralf file using the below command ralgen -uvm -t x regmodel Uvmral.ralf -c bF  for field coverage This generates regmodel.sv file with covergroups showing bit_level_coverage and field_coverage groups. When I compile and run my testcase, I see bit_coverage is 0% hit but my field_coverage is >0%(I mean I see coverage on field). In my env I am doing set_coverage(UVM_CVR_ALL) but generated regmodel.sv contains specific UVM_CVR_FIELD_VALS and UVM_CVR_REG_BITS covergroups for each reg
  3. i am just using uvm_reg_bit_bash_seq which is with UVM package. monitoring is not done in my defined sequence. this is how i am using it. uvm_reg_bit_bash_seq pie8_ral_seq = uvm_reg_bit_bash_seq::type_id::create("pie8_ral_seq",this) pie8_ral_seq.model = tbEnv.regmodel; pie8_ral_seq.start(null);
  4. Its a read/write bit, this is the first bit of bit bash. yes DUT is idle, and i am able to see writing value 1 to each bit twice in waveform.
  5. uvm_reg_bit_bash_seq always writes value 1, both the times and always keep the exp value to default value of the register. in this sequence bash_kth_bit task i tried just adding rg.set(val) after write is done. it started working fine. i am using uvm-1.0p1 version of UVM package. Does anyone face this issue in uvm-1.1 also? or is it fixed in new version?
  6. rajiv, solution is same as jeffs reply. dont modify the transaction once data is present.
  7. I am trying to create and RAL for AHB bus. My adapter is not able to read the data correctly. My env uses a synopsis AHB VIP.VIP is configured to 32bit address and data. Write is working with this adapter. Read is delayed by one clock cycle which is making read data from adapter as 0’s always. Here is the sim.log displays from adapter: @ 78400823500: reporter [RAL ADAPTER] reg2bus rw.DATA = 00, rw.ADDRESS = 20c @ 78400823500: reporter [RAL ADAPTER] reg2bus tr.DATA = 00, tr.ADDRESS = 20c @78400823500 address is on reg2bus @ 78412835500: reporter [RAL ADAPTER] bus2reg rw.DATA = 00, rw.
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