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Trigger a method on two signals


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I want to know if a method can be triggered only when two two signals or ports are high.

To be specific, I want my module (Write_Data_out) to output data only when all of the following conditions hold:

1. Clock positive edge is detected

2. Address Valid (AV) signal is low

3. Read (RD) is High. 

The method (Write_Data_out) must not be triggered otherwise.

I cannot find any information or examples to do this.

The only way i see this that I declare a method sensitive to clock and in the method, do processing if the 

AV is low

RD is high

else return from method

the && operator does not support sc_event_finder and << does not support bool (if << operator for sensitive supported boo, i could do something like this

clk.posedge()& (!AV.read()) && (RD.read). where AV and RD are sc_in<bool>

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Your observations are correct, but it really is not a problem. Even in Verilog you cannot do differently:

// Verilog/SystemVerilog
module Design( input CLK, AV, RD );
  always @(posedge CLK)
    if ( AV == 0 && RD == 1 ) begin
      WriteDataOut(...);
    end
endmodule

So in SystemC:

#include <systemc>
using namespace sc_core; //< Simplifying bad practice
SC_MODULE(Design) {
  sc_in<bool> CLK, AV, RD
  SC_CTOR(Design) {
    SC_METHOD(main_method);
    sensitive << CLK.pos();
  }
  void main_method() {
    if( not AV->read() && RD->read() ) {
      WriteDataOut(...);
    }
  }
};

Event driven simulators trigger on events, not values.

In case you get distracted, here is a solution that will not work despite appearances:

#include <systemc>
using namespace sc_core; //< Simplifying bad practice
SC_MODULE(Design) {
  sc_in<bool> CLK, AV, RD
  SC_CTOR(Design) {
    SC_METHOD(main_method);
  }
  void main_method() {
    next_trigger( CLK->posedge_event() & AV->posedge_event() & RD->negedge_event()); //< not what you might think
    if( not AV->read() && RD->read() ) {
      WriteDataOut(...);
    }
  }
};

The & in the next trigger means that invocation will occur when all three events have happened; however, there is no requirement on when they occur. In other words, they won't be lined up correctly.

 

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