Instantiating SystemC module in Verilog: not seeing 1-cycle flop latency

[coderoo]

I'm testing the instantiation of a SystemC module in a Verilog testbench using VCS. I expect to see a 1-cycle output delay due to flop latency. However, the SystemC module produces the output at the same cycle as the input.

The module is a simple counter.

The entire code is visible here:

https://www.edaplayground.com/x/7reZ

Thank you.

[David Black]

Your problem is in the verilog because you created a race condition. Replace the $display with $strobe to see the proper settled condition of the signals.

See https://www.edaplayground.com/x/9KdZ

Perhaps you have not been formally trained in the semantics of event driven simulation.

[coderoo]

Hi David,

Thanks for explaining the issue and providing the fix. Yes, I do need to understand how the simulator handles this. Would you be able to provide any reading references?

[maehne]

@coderoo: As a start, you can have a look to this blog post by Chethan. If you want to avoid having to deal with non-deterministic simulation results due to race conditions in the future, you may consider switching from Verilog to VHDL. 😉