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Instantiating SystemC module in Verilog: not seeing 1-cycle flop latency


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I'm testing the instantiation of a SystemC module in a Verilog testbench using VCS. I expect to see a 1-cycle output delay due to flop latency. However, the SystemC module produces the output at the same cycle as the input.

The module is a simple counter.

The entire code is visible here:

https://www.edaplayground.com/x/7reZ

Thank you.

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