coderoo Posted April 29, 2021 Report Share Posted April 29, 2021 I'm testing the instantiation of a SystemC module in a Verilog testbench using VCS. I expect to see a 1-cycle output delay due to flop latency. However, the SystemC module produces the output at the same cycle as the input. The module is a simple counter. The entire code is visible here: https://www.edaplayground.com/x/7reZ Thank you. Quote Link to comment Share on other sites More sharing options...
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