UVM reg predefined sequence

[abhishekyadav123]

1. Defned a class "my_reg" extended from uvm_reg_sequence.

2. Created an object of "uvm_reg_hw_reset_seq"-

uvm_reg_hw_reset_seq reg_seq;

`uvm_create(reg_seq)

3.Initiated the sequence by calling its start method.

reg_seq.start(null) //Default sequencer is already set in the env

Now I came across with a UVM_ERROR which reflects "Not block or system specfied to run sequence on".

Please guide me about the correct usage of the UVM reg predefined sequences.

[lisakb1963]

Here is what I did: It seems like you may not be setting the model correctly, in you req_seq

From the calling test:

//declaration of the sequence that does the built-in
set_resets_seq rst_seq;

// In the build_phase
rst_seq = set_resets_seq::type_id::create("set_resets_seq", this);
...
rst_seq.model = yapp_model;  // you have to give the sequence a model to run on.  Since I am re-using it, I using the start method at a test as a wrapper.

//In the run_phase of the test:
rst_seq.start(hbus_seqr);  // this is the bus that I want to run the front door register sequence on.

In my set_resets_seq:

class set_resets_seq extends uvm_reg_sequence();
rdb_pkg::yapp_am model;

    logic [7:0] data;
    uvm_status_e status;
    uvm_reg_sequence rseq;

 `uvm_object_utils(set_resets_seq)
   function new (string name="set_resets_seq");
       super.new(name);
   endfunction

   function connect_phase (uvm_phase phase);
     uvm_config_db#(rdb_pkg::yapp_am)::set(uvm_root::get(),"*set_resets_seq*",
        "*model*", model);
   endfunction

   virtual task body();

      rseq = uvm_reg_hw_reset_seq::type_id::create("rseq");
      rseq.model = model;
      `uvm_info("Calling Built in reset test","Starting Reset Test",UVM_LOW)
       rseq.start(null);

  endtask
endclass

I made a wrapper sequence -- just for my testing. Because I have a lot of experimental reg sequences

You can probably just have the seq_reset_seq, But:

1) You have to give it a model from somewhere, you can always retrieve from the database.

2) You need to give it a front door bus sequencer to run on (if it's not in already defaulted)

For a simple version of what you are doing:

class smoke_test extends uvm_test
smoke_env env;  // assume your model is in here too

   task run_task(uvm_phase phase);

      uvm_reg_hw_reset_test reg_seq = new();
  
     phaise.raise_objection(this, "Running hw reset_test");
     reg_seq.model = env.model;
     reg_seq.start(null);   // assuming the default sequencer has been set up for the frontdoor
     phase.drop_objection(this, "End of hw reset test");

   endtask

endclass

Edited March 24, 2012 by lisakb1963
Mistake in code #2

[abhishekyadav123]

Thanks.

Setting of the model was missing in my code.

[raghavendrap]

Thanks.

Setting of the model was missing in my code.

Hello guys,

I tried to do the same thing, but i am seeing below warnings, please let me know how to overcome these.

UVM_WARNING */uvm/src/reg/uvm_reg_map.svh(1280) @ 0: reporter [RegModel] map 'uvm_reg_map' does not seem to be initialized correctly, check that the top register model is locked()

UVM_WARNING */uvm/src/reg/uvm_reg_map.svh(1280) @ 0: reporter [RegModel] map 'uvm_reg_map' does not seem to be initialized correctly, check that the top register model is locked()

Thanks

Raghavendra

[lisakb1963]

In the build_phase where you are building your model did you do a:

model.lock();

This needs to be done before any usage