bitdiver Posted February 10, 2021 Report Share Posted February 10, 2021 Hello, I would like to study access times on a combination of memories, and instead of verilog, I think it can be interesting to run a SystemC model. For my study, I would like to have the IOs as a parameter and the addresses (= number of words). However, I am bit confused where to start with the definition of SC_MODULE. How would I declare the address and data bus, sc_in<bool> is a single signal, how to declare the bus with N signals? How would it be possible to have latency of the memory as a parameter for modelling the access time? Thanks! Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.