Example for simple memory blocks

[bitdiver]

Hello,

I would like to study access times on a combination of memories, and instead of verilog, I think it can be interesting to run a SystemC model.

For my study, I would like to have the IOs as a parameter and the addresses (= number of words).

However, I am bit confused where to start with the definition of SC_MODULE.

How would I declare the address and data bus, sc_in<bool> is a single signal, how to declare the bus with N signals?

How would it be possible to have latency of the memory as a parameter for modelling the access time?

Thanks!

[Eyck]

Addresses and data should be modelled as sc_uint<WIDTH> since this forms one signal carrying events. Having a (sc_)vector creates n-signals with n events which adds simulation overhead. It should look like:

sc_core::sc_signal<sc_dt::sc_uint<32>> data_i;

The latency setting can either be set as a constructor argument or a SystemC CCI parameter.

[bitdiver]

Thanks eyck, that works.