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bitdiver

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  1. Hello, I would like to study access times on a combination of memories, and instead of verilog, I think it can be interesting to run a SystemC model. For my study, I would like to have the IOs as a parameter and the addresses (= number of words). However, I am bit confused where to start with the definition of SC_MODULE. How would I declare the address and data bus, sc_in<bool> is a single signal, how to declare the bus with N signals? How would it be possible to have latency of the memory as a parameter for modelling the access time? Thanks!
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