Strange behavior of simple RL circuit -- help please

[dakupoto]

Could some SystemC-AMS guru please

help ? I have a simple RL circuit, excited

by a square wave. A current controlled

current source (sca_eln::sca_cccs) is

connected in parallel with voltage

controlled voltage source(sca_eln::sca_vcvs)

at the end of the inductor away from

the resistor. The voltage and current

outputs of both the controlled sources

are measured, While the current output

changes as expected, the voltage output

is zero, which is very odd. The attached

plot shows the square wave excitation

pulse and the inductor current output.

Given that voltage across the inductor

is L*(dI/dt) could someone suggest

what the problem might be ? I have

tried to measure the voltage directly (

no vcvs) but the results are the same.

[maehne]

Hello,

it's hard to tell where's your problem. Your description of the circuit itself is not very clear. The "attached plot" mentioned in the post is missing. Post a minimal and self-contained code example so that we can see what you've done. In general, the ELN MoC gives correct results for linear electrical circuits. Therefore, I suspect your netlist might not be correct.

That said, I would like to insist on the fact that for pure circuit-level modeling a language such as SPICE, VHDL-AMS, or Verilog-AMS might be more suitable. The power of SystemC AMS lies on higher system-level modeling done using primarily the TDF model of computation in conjunction with regular SystemC discrete event and TLM modeling techniques.

Best regards,

Torsten Maehne

[dakupoto]

Hello,

I fully agree with your comments above, however may I point out.

1. SPICE model already works, and this is an attempt to create a

high level model.

2. The circuit is very simple, a L and a R in series, with a voltage

controlled voltage source and a current controlled current source

connected in parallel to the L node other than the one connected

to the R. The controlled current source output looks as expected,

but the controlled voltage source output is zero. source The RL is

excited with a square wave pulse train.

Self-contained source code follows shortly

.

[maehne]

Hello,

I fully agree with your comments above, however may I point out.

1. SPICE model already works, and this is an attempt to create a

high level model.

I agree, if this model is meant as an intermediary step. Just changing the modeling language doesn't give you a higher-level model. You'll also need to simplify your model to raise the actual level of abstraction sacrificing precision for speed.

2. The circuit is very simple, a L and a R in series, with a voltage

controlled voltage source and a current controlled current source

connected in parallel to the L node other than the one connected

to the R. The controlled current source output looks as expected,

but the controlled voltage source output is zero. source The RL is

excited with a square wave pulse train.

Self-contained source code follows shortly

We'll wait for your source code, as a textual description of your circuit is not sufficient to diagnose the source of your problem.

[dakupoto]

Sorry for the delay. The following is the self-contained source code.

In fact it has a module that formats output for plotting with Gnuplot.

I guess there is some subtle bug, which does not affect the

compilation or execution, but does not generate the correct output.

Here we go.

#ifndef REGENMOT_H

#define REGENMOT_H

#include <systemc-ams>

/* Square wave excitation pulse train */

SCA_TDF_MODULE(syncpulse)

{

sca_tdf::sca_de::sca_out<double> sigout;

double currtime;

double freq;

double value;

double plsvalue;

void set_attributes()

{

sigout.set_timestep(1.0, sc_core::SC_MS);

sigout.set_rate(1);

}

void processing()

{

currtime = sc_core::sc_time_stamp().to_seconds();

value = plsvalue*cos(6.28*freq*currtime) -

plsvalue*cos(3.0*6.28*freq*currtime)/3 +

plsvalue*cos(5.0*6.28*freq*currtime)/5 -

plsvalue*cos(7.0*6.28*freq*currtime)/7 +

plsvalue*cos(9.0*6.28*freq*currtime)/9 -

plsvalue*cos(11.0*6.28*freq*currtime)/11 +

plsvalue*cos(13.0*6.28*freq*currtime)/13 -

plsvalue*cos(15.0*6.28*freq*currtime)/15 +

plsvalue*cos(17.0*6.28*freq*currtime)/17 -

plsvalue*cos(19.0*6.28*freq*currtime)/19 +

plsvalue*cos(21.0*6.28*freq*currtime)/21 -

plsvalue*cos(23.0*6.28*freq*currtime)/23 +

plsvalue*cos(25.0*6.28*freq*currtime)/25 -

plsvalue*cos(27.0*6.28*freq*currtime)/27 +

plsvalue*cos(29.0*6.28*freq*currtime)/29 -

plsvalue*cos(31.0*6.28*freq*currtime)/31 +

plsvalue*cos(33.0*6.28*freq*currtime)/33 -

plsvalue*cos(35.0*6.28*freq*currtime)/35 +

plsvalue*cos(37.0*6.28*freq*currtime)/37 -

plsvalue*cos(39.0*6.28*freq*currtime)/39 +

plsvalue*cos(41.0*6.28*freq*currtime)/41 -

plsvalue*cos(43.0*6.28*freq*currtime)/43 +

plsvalue*cos(45.0*6.28*freq*currtime)/45 -

plsvalue*cos(47.0*6.28*freq*currtime)/47 +

plsvalue*cos(49.0*6.28*freq*currtime)/49 -

plsvalue*cos(51.0*6.28*freq*currtime)/51;

sigout.write(value);

}

SCA_CTOR(syncpulse):value(0.0){ }

~syncpulse(){ }

};

/* Remove negative value pulses from square wave pulse train */

SCA_TDF_MODULE(onebitadc)

{

sca_tdf::sca_de::sca_in<double> sigin;

sca_tdf::sca_de::sca_out<double> sigout;

double currvalue;

void set_attributes()

{

sigin.set_timestep(1.0, sc_core::SC_MS);

sigout.set_timestep(1.0, sc_core::SC_MS);

sigin.set_rate(1);

sigout.set_rate(1);

}

void processing()

{

currvalue = sigin.read();

if(currvalue < 0.0) sigout.write(0.0);

else sigout.write(currvalue);

}

SCA_CTOR(onebitadc):currvalue(0.0){ }

~onebitadc(){ }

};

SC_MODULE(armtest)

{

sc_core::sc_in<double> sigin0;

sc_core::sc_out<double> sigout0;

sc_core::sc_out<double> sigout1;

sca_eln::sca_de::sca_vsource vin0;

sca_eln::sca_de::sca_isink iout0;

sca_eln::sca_de::sca_vsink vout0;

sca_eln::sca_l larm;

sca_eln::sca_r rarm;

sca_eln::sca_cccs cccs0;

sca_eln::sca_vcvs vcvs0;

sca_eln::sca_node n1;

sca_eln::sca_node n2;

sca_eln::sca_node n3;

sca_eln::sca_node n4;

sca_eln::sca_node n5;

sca_eln::sca_node_ref gnd;

SC_CTOR(armtest):iout0("iout0", 1.0),

vin0("vin0", 1.0),

vout0("vout0", 1.0),

cccs0("cccs0", 10.0),

vcvs0("vcvs0", 10.0),

larm("larm", 0.065),

rarm("rarm", 0.5)

{

iout0.set_timestep(1.0, sc_core::SC_MS);

vin0.set_timestep(1.0, sc_core::SC_MS);

vout0.set_timestep(1.0, sc_core::SC_MS);

cccs0.ncp(n3);

cccs0.ncn(gnd);

cccs0.np(n4);

cccs0.nn(gnd);

iout0.outp(sigout0);

iout0.p(n4);

iout0.n(gnd);

vcvs0.ncp(n3);

vcvs0.ncn(gnd);

vcvs0.np(n5);

vcvs0.nn(gnd);

vin0.inp(sigin0);

vin0.p(n1);

vin0.n(gnd);

vout0.outp(sigout1);

vout0.p(n5);

vout0.n(gnd);

rarm.p(n1);

rarm.n(n2);

larm.p(n2);

larm.n(n3);

}

~armtest(){ }

};

/* Format output for plotting with GNUPLOT */

SC_MODULE(ssctracedbldbl)

{

sc_core::sc_in<double> din0;

sc_core::sc_in<double> din1;

std::ofstream output;

double currtime;

double d0;

double d1;

void ssctracedbldbl_proc0()

{

while(1)

{

wait();

currtime = sc_core::sc_time_stamp().to_seconds();

d0 = din0.read();

d1 = din1.read();

output << std::scientific << currtime << " " << d0 << " " << d1 << std::endl;

}

}

SC_CTOR(ssctracedbldbl)

{

output.open(name(), std::ios::out);

SC_THREAD(ssctracedbldbl_proc0);

sensitive << din0 << din1;

}

~ssctracedbldbl() { output.close(); }

};

#endif

#include "regenmot.h"

int sc_main(int argc, char **argv)

{

sc_core::sc_signal<double> sigin0;

sc_core::sc_signal<double> sigin1;

sc_core::sc_signal<double> sigout0;

sc_core::sc_signal<double> sigout1;

onebitadc one_bit_adc("one_bit_adc");

syncpulse sync_pls("sync_pls");

armtest arm_test("arm_test");

ssctracedbldbl trregen_tmp("tr_regen");

sync_pls.sigout(sigin0);

sync_pls.plsvalue = 50.0;

sync_pls.freq = 5000.0;

one_bit_adc.sigin(sigin0);

one_bit_adc.sigout(sigin1);

arm_test.sigin0(sigin1);

arm_test.sigout0(sigout0);

arm_test.sigout1(sigout1);

trregen_tmp.din0(sigin1);

trregen_tmp.din1(sigout0);

sc_core::sc_start(5000.0, sc_core::SC_MS);

sc_core::sc_stop();

return 0;

}

[maehne]

Hello,

thanks for sending the source code. Without running your model, I can see from it that SystemC-AMS is right, when it calculates vout to always zero. The reason is that your vcvs0 input is connected in parallel to the cccs0 input, i.e., from n3 to gnd. As the cccs0 input shortcuts n3 to ground, the voltage drop is always zero. I guess you meant to measure the voltage across the inductor, from n2 to gnd or n2 to n3.

By the way, you don't need to decouple the voltage and current sinks from the electrical circuit. They're considered as ideal and therefore won't influence your circuit behavior.

Regards,

Torsten Maehne