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set sc_core::sc_in<bool>

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Let me start by observing that you probably don't want to initialize an input port. After all, inputs observe information from outside the module. So I will assume you mean an output port. If need be, you could change to use an sc_inout<T> port, but you might create a nasty race condition.

The cleanest and most general approach is to write to the port during the start_of_simulation phase. How? Just create a override method, void sc_start_of_simulation(void), in your module.

SC_MODULE( Example )
  sc_out<bool> oport{"oport"};
  sc_signal<int> local_sig{"local_sig"};
  void sc_start_of_simulation( void )
    oport->write( false ); // initialize an external signal via a port
    local_sig.write( 42 ); // initialize an internal signal
  ... the rest of your module ...



One other thing, I need to clear up a misconception: SystemC ports do not have a value despite the unfortunate presence of the overloaded operator=. The value that you are thinking comes from the port, actually comes from the channel it is connected to. In the case of sc_in<T> and sc_out<T>, the channels are specifically sc_signal<T>. Also, a channel itself is not data. Channels are vehicles for communication and synchronization. When you write to an sc_signal, you are depositing a value into an internal buffer, the future value buffer. When you read from an sc_signal, you are obtaining the value from another buffer, the current value. How and when the future value gets copied to the current value, is the subject of a deeper idea.

For sc_signal channels, there used to be special method, init, but that is not standard. It is also the case that a constructor exists in the Proof-of-Concept implementation with a second constructor argument for initialization; however, this is also not yet standardized. So I would avoid either of these approaches.


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Okay, It is clear that I mixwd things!!

Thank you very much for your reply, many things are clarified now.

Actually what I am doing is that I have a module, this module has an input port (sc_in reset) and I made a top module (for testing) and created a that module in it, what I want to do now is to bind a signal to this reset port to be able to reset this module by writing 0 to the signal (reset is active low).

What I think that I should do now is to make sc_signal<T> and to bind it to the reset port, is this right ?


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