IChip Posted March 4, 2012 Report Share Posted March 4, 2012 Hi experts, Why is phase_ready_to_end called more than once in codes below? class top extends uvm_test; `uvm_component_utils(top) function new(string name="top",uvm_component parent=null); super.new(name,parent); endfunction function void build_phase(uvm_phase phase); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); #10; phase.drop_objection(this); endtask task delay_to_end(uvm_phase phase); #1; `uvm_info(get_name(),$sformatf("Now to end %s...",phase.get_name()),UVM_LOW) phase.drop_objection(this); endtask function void phase_ready_to_end(uvm_phase phase); if(phase.get_name == "main")begin `uvm_info(get_name(),"Not yet to end...",UVM_LOW) phase.raise_objection(this); fork begin #1; this.delay_to_end(phase); end join_none end endfunction function void phase_started(uvm_phase phase); if(phase.get_name == "main") `uvm_info(get_name(),"main_phase is started...",UVM_LOW) endfunction function void phase_ended(uvm_phase phase); if(phase.get_name == "main") `uvm_info(get_name(),"main_phase is ended...",UVM_LOW) endfunction endclass sim log: UVM-1.1 (C) 2007-2011 Mentor Graphics Corporation (C) 2007-2011 Cadence Design Systems, Inc. (C) 2006-2011 Synopsys, Inc. (C) 2011 Cypress Semiconductor Corp. ---------------------------------------------------------------- UVM_INFO @ 0: reporter [RNTST] Running test top... UVM_INFO test7_phrdytoend.sv(84) @ 0: uvm_test_top [uvm_test_top] main_phase is started... UVM_INFO test7_phrdytoend.sv(71) @ 0: uvm_test_top [uvm_test_top] Not yet to end... UVM_INFO test7_phrdytoend.sv(65) @ 2: uvm_test_top [uvm_test_top] Now to end main... ........................... UVM_INFO test7_phrdytoend.sv(71) @ 34: uvm_test_top [uvm_test_top] Not yet to end... UVM_INFO test7_phrdytoend.sv(65) @ 36: uvm_test_top [uvm_test_top] Now to end main... UVM_INFO test7_phrdytoend.sv(71) @ 36: uvm_test_top [uvm_test_top] Not yet to end... UVM_INFO test7_phrdytoend.sv(65) @ 38: uvm_test_top [uvm_test_top] Now to end main... UVM_INFO test7_phrdytoend.sv(89) @ 38: uvm_test_top [uvm_test_top] main_phase is ended... Thanks. Quote Link to comment Share on other sites More sharing options...
mastrick Posted March 4, 2012 Report Share Posted March 4, 2012 phase_ready_to_end() is called whenever the total objection count for the current phase decrements to 0. If the objection is raised and dropped in phase_ready_to_end(), it will be called again. To avoid endless loops, there is a maximum count of phase_ready_to_end() that defaults to 20. yemingguang 1 Quote Link to comment Share on other sites More sharing options...
IChip Posted March 5, 2012 Author Report Share Posted March 5, 2012 OK, thanks. Can you help to explain the simulation log and why is simulation finished at time 38? Quote Link to comment Share on other sites More sharing options...
dave_59 Posted March 5, 2012 Report Share Posted March 5, 2012 The code actually limits the count to < 20, so that is 19 iterations. It takes 2 time units each to drop the objection to end main_phase, so that is 2*19 = 38. The 10 time unit delay to drop the objection to end the run_phase is in parallel to the main_phase. Quote Link to comment Share on other sites More sharing options...
IChip Posted March 6, 2012 Author Report Share Posted March 6, 2012 Thank dave. Finally i found in in uvm_phase.svh. int unsigned max_ready_to_end_iter = 20;For every type of phase, phase_ready_to_end will be iterated for 19 times. After this iteration, all forks will be killed. is this arg configurable? Is there any way to set this arg to 2 and make it run once? Thanks. Quote Link to comment Share on other sites More sharing options...
IChip Posted March 6, 2012 Author Report Share Posted March 6, 2012 Hi dave, May I ask another question? When use the red line below, simulation will be ended at time 2. In this case, why is run_phase block also killed? Thanks. task run_phase(uvm_phase phase); phase.raise_objection(this); #10; phase.drop_objection(this); endtask task delay_to_end(uvm_phase phase); #1; `uvm_info(get_name(),$sformatf("Now to end %s...",phase.get_name()),UVM_LOW) phase.drop_objection(this); endtask function void phase_ready_to_end(uvm_phase phase); static int done = 0; if(done)return; [COLOR="Red"] //if(phase.get_name == "main")begin[/COLOR] if(phase.get_name == "run")begin `uvm_info(get_name(),"Not yet to end...",UVM_LOW) phase.raise_objection(this); fork begin #1; this.delay_to_end(phase); done = 1; end join_none end endfunction Quote Link to comment Share on other sites More sharing options...
dave_59 Posted March 6, 2012 Report Share Posted March 6, 2012 Are you sure simulation ends at time 2? It ended at time 10 for me after the main phase ends at time 2. Also, I see you found a solution to your once through problem. You should avoid the use of static variables. You just need to make done a class member. Quote Link to comment Share on other sites More sharing options...
IChip Posted March 7, 2012 Author Report Share Posted March 7, 2012 Thanks Simulation ended at time 10. Quote Link to comment Share on other sites More sharing options...
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