iamgame Posted August 20, 2020 Report Share Posted August 20, 2020 Hi All, I coded up (in TLM) few modules for my SoC (cache mem, interconnects, dma engines etc). I have mostly used simple_initiator_socket and simple_target_sockets for all of my SoC components. I'm modelling for cycle accurate comparison with RTL. My aim is to correlate model with RTL design - in terms of cycles consumed, peak/avg bandwidth/latencies at internal and external memories. What is best way to extract, log and aggregate this information ? Is accumulating delays and time info across API calls like simple_initiator_socket::nb_transport_fw/bw() best way to do it ? Are there TLM APIs which aggregates such information over life cycle of simulation run ? After we get all the info rolled up into final numbers, what metrics (e.g. avg cycle / mem req) are typically compared between TLM and RTL design ? Are there some open source designs where model and design are compared ? Thanks Quote Link to comment Share on other sites More sharing options...
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