In case of size of the register is greater than the width of the address block, How access the register?

[Suhyun]

Hi, I have some question about access the register below case...

[ip-xact information]
- slave interface. bitInLau : 8
- addressblock width : 16
- addressUnitBits        : 8
  - register name A:
      - register offset : 0
      - register size : 32
  - register name B:
      - register offset : 1
      - register size : 32

 

Q1)  Does the above description have any problem in the ip-xact standard?

Q2) In case of the above description, maximum single transfer size is 16. Because address block width is 16. Is it right?

Q3) I know as below. Is it right?

addr_offset@ip-xact       address @ slave interface           access register
              0x0                                 0x0                                           A[15:0]
              0x1                                 0x2                                           B[15:0]

 Q4) How can access the register A[31:16] ?

Thanks & regards,
Suhyun

[Suhyun]

The above descriptoin have probelm about SCR7.5... (The size of any register shall be no greater than the width of the containing address block.)
[ip-xact information]
- slave interface. bitInLau : 8
- addressblock width : 16
- addressUnitBits        : 8
  - register name A_0:
      - register offset : 0
      - register size : 16
  - register name A_1:
      - register offset : 1
      - register size : 16
  - register name B_0:
      - register offset : 2
      - register size : 16 
  - register name B_1:
      - register offset : 3
      - register size : 16

addr_offset@ip-xact       address @ slave interface           access register
              0x0                                 0x0                                           A_0
              0x1                                 0x2                                           A_1 
              0x2                                 0x4                                           B_0
              0x3                                 0x6                                           B_1

Anyway, ignore the above question.
Q1)  Is value of addressblock's width same as data bus width of the slave interface?
        ex) If addressblock width =16,  data bus(apb_wdata, apb_rdata) width is 16. is it right?

[kock]

Hi Suhyun,

Your register descriptions are not valid. You have addressUnitBits set to 8 meaning that the unit of addressing is 8 bits. That means that your register offset should 0, 2, 4, … In your example, they are 0, 1, 2, … while the registers are 16 bits. That means register 0 occupies bits 0 to 15, register 1 occupies bits 8 to 23, and so on. Hence, they overlap.

The address block width indicates the maximum number of bits that can be accessed in a single transaction. The data bus width can be different. Your bus interface contains port maps. The logical ports in the port maps can have qualifiers. One of the qualifiers is isData. So you can look at the number of bits of the physical port that is mapped to the logical port with the isData qualifier.

Best regards,
Erwin

[Suhyun]

Hi Erwin,

Thanks for your answer.
Your answer is very helpful to me.

 

I modified register description based on your answer. (addressUnitBits 8 -> 16)

Q1)Is the description below right?

[ip-xact information]
- slave interface. bitInLau : 8
- addressblock width : 16
- addressUnitBits        : 8 -> 16
  - register name A_0:
      - register offset : 0
      - register size : 16
  - register name A_1:
      - register offset : 1
      - register size : 16
  - register name B_0:
      - register offset : 2
      - register size : 16 
  - register name B_1:
      - register offset : 3
      - register size : 16

addr_offset@ip-xact       address @ slave interface           access register
              0x0                                 0x0                                           A_0[15:0]
              0x1                                 0x2                                           A_1[15:0]
              0x2                                 0x4                                           B_0[15:0]
              0x3                                 0x6                                           B_1[15:0]

 

Q2) If isData is not define,  addressblock's  width same as data bus width. Is it right?

 

[kock]

Hi Suhyun,

Your description defines the addressBlock width as 16. If there is no isData qualifier or no port map, then data width of the bus interface is not documented. You cannot assume that it is the same as the addressBlock width. For instance, the data bus width may be 8 in which case you need 2 transactions to read the content of a register.

Best regards,
Erwin