ZhangRan Posted December 5, 2019 Report Share Posted December 5, 2019 Hi, I am a noob of systemC and tlm modeling. I just go through same example of systemC TLM modeling, such as “”simple_bus“”. I am trying develop a TLM processor model. This processor is high performance out of oroder processor(more than 10 stages). At first, i am focusing on the performance affected by branch prediction. Is there any examples related to TLM processor modelling? Thank you very much. Quote Link to comment Share on other sites More sharing options...
ZhangRan Posted December 5, 2019 Author Report Share Posted December 5, 2019 Can someone give me some idea of CPU TLM modeling. Thank you very much. Quote Link to comment Share on other sites More sharing options...
Eyck Posted December 5, 2019 Report Share Posted December 5, 2019 There is no such thing as CPU TLM modeling. Usually you write a C/C++ processor model with the needed accuracy (instruction accurate, cycle approximate, cycle accurate) and wrap it in a way that you translate memory accesses into TLM socket accesses. Along with that you need to manage to syncronization of the time of your model and the SystemC time (to run e.g. in loosly timed mode). Another task is to take the returned execution time of the bus accesses into account for the execution of the CPU model. This involves also the selection and implementation of the accesses (DMI & blocking or non-blocking). You can find a complete example of an instruction accurate VP at https://git.minres.com/DVCon2018/RISCV-VP (or https://git.minres.com/VP/RISCV-VP which is a newer version). The wrapper for the C++ model in SystemC can be found at https://git.minres.com/DVCon2018/RISCV-VP/src/branch/develop/riscv.sc/incl/sysc/core_complex.h To put it straight: doing this correctly is a non-trivial task as it is the implementation of a micro-architecture model of a CPU. One option is to build an instruction accurate ISS and add a microarchitecture model like it is done in the ESECS project (https://github.com/MIPS/esesc) BR swami-cst, ZhangRan and Mik 2 1 Quote Link to comment Share on other sites More sharing options...
ZhangRan Posted December 5, 2019 Author Report Share Posted December 5, 2019 2 hours ago, Eyck said: There is no such thing as CPU TLM modeling. Usually you write a C/C++ processor model with the needed accuracy (instruction accurate, cycle approximate, cycle accurate) and wrap it in a way that you translate memory accesses into TLM socket accesses. Along with that you need to manage to syncronization of the time of your model and the SystemC time (to run e.g. in loosly timed mode). Another task is to take the returned execution time of the bus accesses into account for the execution of the CPU model. This involves also the selection and implementation of the accesses (DMI & blocking or non-blocking). You can find a complete example of an instruction accurate VP at https://git.minres.com/DVCon2018/RISCV-VP (or https://git.minres.com/VP/RISCV-VP which is a newer version). The wrapper for the C++ model in SystemC can be found at https://git.minres.com/DVCon2018/RISCV-VP/src/branch/develop/riscv.sc/incl/sysc/core_complex.h To put it straight: doing this correctly is a non-trivial task as it is the implementation of a micro-architecture model of a CPU. One option is to build an instruction accurate ISS and add a microarchitecture model like it is done in the ESECS project (https://github.com/MIPS/esesc) BR Thank you so much, I will working hard on your example. Quote Link to comment Share on other sites More sharing options...
User 128 Posted April 10 Report Share Posted April 10 On 12/5/2019 at 2:13 PM, Eyck said: There is no such thing as CPU TLM modeling. Usually you write a C/C++ processor model with the needed accuracy (instruction accurate, cycle approximate, cycle accurate) and wrap it in a way that you translate memory accesses into TLM socket accesses. Along with that you need to manage to syncronization of the time of your model and the SystemC time (to run e.g. in loosly timed mode). Another task is to take the returned execution time of the bus accesses into account for the execution of the CPU model. This involves also the selection and implementation of the accesses (DMI & blocking or non-blocking). You can find a complete example of an instruction accurate VP at https://git.minres.com/DVCon2018/RISCV-VP (or https://git.minres.com/VP/RISCV-VP which is a newer version). The wrapper for the C++ model in SystemC can be found at https://git.minres.com/DVCon2018/RISCV-VP/src/branch/develop/riscv.sc/incl/sysc/core_complex.h To put it straight: doing this correctly is a non-trivial task as it is the implementation of a micro-architecture model of a CPU. One option is to build an instruction accurate ISS and add a microarchitecture model like it is done in the ESECS project (https://github.com/MIPS/esesc) BR Hi BR, I noticed that the two paths at minres are 404 errored now. Is the github path the replicate of that? https://github.com/vherdt/riscv-vp/tree/master Best Regards, User 128 Quote Link to comment Share on other sites More sharing options...
Eyck Posted April 25 Report Share Posted April 25 They have been further developed and we moved them to github: https://github.com/Minres/TGC-VP https://github.com/Minres/HIFIVE1-VP Quote Link to comment Share on other sites More sharing options...
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