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Register model coverage

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Three things must happen

1) A coverage model must be included in the generated model. See your generator options to ensure this is ON.

2) The register model must be built with the coverage model using uvm_reg::include_coverage(). You appear to have done so.

3) Coverage sampling must be turned on using uvm_reg_block::set_coverage().

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  • 7 months later...

Even i am facing an issue with proper sampling of coverage. I have done all the three things above.

1) Covergroups for each register containing individual coverpoints for each field are present in the model generated by using iregGen

2) I am including uvm_reg::include_coverage("*", UVM_CVR_ALL) in the build_phase of my testcase.

3) I am including void'(<addr_block_instance).set_coverage(UVM_CVR_ALL)) in my body of virtual sequence.

Still i am not getting proper coverage. I am getting correct hits for some of the register read writes while rest are sampled wrongly.

I think the sampling is not happening properly.

I am wondering how to debug this?

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