Jump to content
gyro

How to introduce a delay of 1 Cycle

Recommended Posts

Kindly bear with me if the question is too naive.

I have a SystemC module, and i want to introduce a delay of 1 cycle, how can i do that ?

As per my understanding , something like wait(1, SC_NS) is delay of 1 NS not really a delay of 1 cycle.

Thanks

Share this post


Link to post
Share on other sites

wait(SC_ZERO_TIME);

But perhaps there is more to your question. You probably need to provide some code to get a more comprehensive answer. For example, the above assumes an SC_THREAD process. If you have an SC_METHOD, then you would use:

next_trigger(SC_ZERO_TIME);

combined with some FSM mechanism.

Share this post


Link to post
Share on other sites

I can't put the exact code here, but will try to put the basic idea that i intend to do.

I have testbench, something like : 

class tb : public sc_module {

      sc_in<bool> Rdy;

      sc_out<bool> vld;

     sc_clock m_clk;

     SC_THREAD(run);

    sensitive << m_clk;

};

void run() {

   if vld = false

   // do some stuff

  // no the next rising edge of clk check if rdy is high

  // if yes de-assert vld

  // else wait for rdy to become high

}

I have component say mod to which all these port are tied using some s/g. so the class mod will have port types reverse of tb.

class mod : public sc_module {

    sc_out<bool> Rdy;

      sc_in<bool> vld;

}

It's basic protocol of communication that i am trying to replicate. Master enables Valid for slave, along with other data. Slave when ready enables Rdy s/g. 

Master de-asserts Valid on the next rising edge after i has received Rdy from slave.

even if i add a zero time in the thread i still get the same time as before SC_ZERO_TIME.

What is that i am missing out here ?

void run() {

   if vld = false

   // do some stuff

  wait(SC_ZERO_TIME);

 std::cout << sc_time_stamp().to_string();

  // no the next rising edge of clk check if rdy is high

  // if yes de-assert vld

  // else wait for rdy to become high

}

Share this post


Link to post
Share on other sites
wait(SC_ZERO_TIME);

waits for 1 delta cycle

I guess you want  a clock cycle delay instead.

wait( clock.posedge_event() ); // wait until positive clock edge

wait( clock.negedge_event() ); // wait until negative clock edge

 

Share this post


Link to post
Share on other sites

Thanks,  waiting for both edges of clock work fine.

I have a another question, Let's say i have one SC_THREAD and one SC_METHOD(my_run)

in SC_THREAD i set out port Vld to true

run() {

// do some stuff

Vld.write(true);

// do some stuff

// wait

// check condition if true notify method

}

my_run() {

Vld.write(false);

}

I get a multiple driver error. Can't i access same port from two different process. Is this beacuse of non-deterministic scheduling of process within the same cycle, Vld can be overwrriten with different values ?

 

Share this post


Link to post
Share on other sites
On 9/12/2019 at 11:10 PM, gyro said:

I get a multiple driver error. Can't i access same port from two different process. Is this beacuse of non-deterministic scheduling of process within the same cycle, Vld can be overwrriten with different values ?

It is configurable, see SystemC standard "6.4.4 Reading and writing signals". 

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.


×
×
  • Create New...