find parent port?

[kobiji]

Hi,

I am looking to extract hierarchy and connections within my SystemC module. Currently for an sc_port I can retrieve the bound interfaces and their counts via get_interface() and bind_count() respectively, but I'd also like to know if the sc_port has a parent port and if yes, how to find that parent. I looked at the reference manual but there seems to be no way to do this? 

I am very new to SystemC, so I'd really appreciate your help. Thanks! 

[David Black]

Try get_parent_object() -- IEEE 1666-2011 page 128

[Philipp A Hartmann]

Port-to-port binding is not tracked by SystemC after elaboration is completed.  You can try to restore (or at least approximate) the mapping yourself by checking "overlap" in the get_interface() results across ports and the hierarchical relationship between the ports' parent objects.

[Roman Popov]

I had the same problem when working on connection visualization tool for SystemC, had to hack SystemC kernel to preserve port-to-port connections after elaboration.

What I've found that in many real models some ports are connected through hierarchical boundaries like:

input_port.bind ( mod.submod.other_submod.channel )

So I also had to create "virtual" ports, that do not exist in code, just for visualization. 

[David Black]

I see this question a lot. Perhaps an enhancement idea for a future SystemC. register_port could be augmented by adding a bit of data to channels to record the connecting parent. This would add a small structure (?vector<sc_object*>?), and add a tiny bit prior to start of simulation. Providing a "netlist" helps to confirm everything is connected correctly. Of course it won't for all the connectivity (e.g. a global clock object), but it would go a long way.