shubham_v Posted May 31, 2019 Report Share Posted May 31, 2019 Hi , I was having doubt over using these interfaces defined in diff languages. I am comparing 3 of the inerfaces below as follows: SYSTEM VERILOG - In system verilog as much as i am aware about,we will be declaring a common interface and give the direction for inputs & outputs via modports and driving the blocks with a common clock. SYSTEM C -In system c, we will be inheriting interface from sc_interface,declaring the type of operation required ,that is in turn defined in the required type of channel and then executed. TLM- There are diffrent type of predefined interfaces,which will be used depending on our requirement such as b_transport for LT MODEL,and nb_transport for AT MODEL. My question is, in interfaces we are defining the inputs and ouputs in sys.verilog and connecting them.Then what about in system c and tlm ? Is there any possibility of declaring the inputs in system c and tlm interfaces? What i think is ,as these are already predefined ,so we dont need to alter anything over there in the interfaces. And even if we got to change any thing in the interfaces,complexity might increase ? This is the confusion which i am getting when working with them,please let me know how exactly are they differeing during defining the inputs and outputs . Thanks in advance. Regards, Shubham Quote Link to comment Share on other sites More sharing options...
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