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hi All, Can you please suggest the recommended way to create a SystemC testbench for SystemC model verification?

I looked at UVM SystemC as well, considering that its relatively new, do you suggest using it for a project?  The similarity to UVM makes it easier to adopt. 

thanks, RC

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Hi RC,

 

There are a lot of different options to create a SystemC testbench. UVM is of course broadly used, but might be too heavy or not perfectly suited for your case. Depending on the answers to the questions below, you will get a different recommendation:

  • Which interfaces does the DUT have?
  • What is the complexity of the DUT?
  • Do you need a register model?
  • Does the DUT contain mixed signal functionality?
  • What kind of test scenarios do you envision? Directed / constrained-random?
  • Do you build the testbench from scratch or are you reusing verification components / tests?
  • Do you plan to reuse the tests and/or testbench in other environments, like HDL simulations or in a validation/lab environment?
  • etc.

--

greetz,

Bas

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Thanks Bas, response to questions is posted below:

  • Which interfaces does the DUT have? 

           Multiple interfaces with standard AMBA and a couple of others (non-standardized)

  • What is the complexity of the DUT?

           Relatively complex, most of the operations are predefined and have a standard task to be performed

  • Do you need a register model? yes
  • Does the DUT contain mixed signal functionality? no
  • What kind of test scenarios do you envision? Directed / constrained-random? both 
  • Do you build the testbench from scratch or are you reusing verification components / tests? - from scratch
  • Do you plan to reuse the tests and/or testbench in other environments, like HDL simulations or in a validation/lab environment? 

            SystemC model yes, testbench yes (as much as possible)

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If your testbench environment wasn't limited to SystemC, I'd advice to use UVM-SV with a vendor solution. It would bring you, among other things, standard interface UVCs and constraint-random possibilities.

In your case, you will have to implement a.o. your AMBA UVC(s) which can take quite some effort and can be quite complex. Next to that, the current UVM-SystemC 1.0-beta2 release does not yet contain constraint-random functionality, although the combination of UVM-SC with CRAVE (Constraint RAndom Verification Environment) has been presented at DVCon Europe 2018.

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