R_C Posted February 23, 2019 Report Share Posted February 23, 2019 hi All, Can you please suggest the recommended way to create a SystemC testbench for SystemC model verification? I looked at UVM SystemC as well, considering that its relatively new, do you suggest using it for a project? The similarity to UVM makes it easier to adopt. thanks, RC Quote Link to comment Share on other sites More sharing options...
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