R_C

I agree with Bas, recently integrated a model to UVM driver/component using standard TLM socket (simple_initiator_socket), tried with TLM put port first but didn't work. -RC

Thanks Stephan, your comments were helpful. Examples work with the default version though i still need to figure out why it didn't work for gcc 4.1.2, LD_LIBRARY_PATH is correct for gcc but not sure about binutils PATH, will debug it further but at least i know that the problem is in setup, not the tar/code (which was anyways less likely).

hi All, I am trying to compile UVM-SC in linux (gcc version 4.1.2, SUSE Linux Enterprise Desktop 11 SP4) but it fails at 'gmake check' with the below error: ---------------------------------------------------------------------- sc_main.cpp:(.text._ZN3top11build_phaseERN3uvm9uvm_phaseE[top::build_phase(uvm::uvm_phase&)]+0x29): undefined reference to `std::basic_ostream<char, std::char_traits<char> >& std::__ostream_insert<char, std::char_traits<char> >(std::basic_ostream<char, std::char_traits<char> >&, char const*, long)' ../../s

Thanks Bas, response to questions is posted below: Which interfaces does the DUT have? Multiple interfaces with standard AMBA and a couple of others (non-standardized) What is the complexity of the DUT? Relatively complex, most of the operations are predefined and have a standard task to be performed Do you need a register model? yes Does the DUT contain mixed signal functionality? no What kind of test scenarios do you envision? Directed / constrained-random? both Do you build the testbench from scratch or are you reusing veri

hi All, Can you please suggest the recommended way to create a SystemC testbench for SystemC model verification? I looked at UVM SystemC as well, considering that its relatively new, do you suggest using it for a project? The similarity to UVM makes it easier to adopt. thanks, RC