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Possible bug in UVM IEEE

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Hi all,

I found a possible bug in the UVM register layer. It is in file uvm_reg_field.svh at line 728-730:

   // Assume that the entire field is enabled
   if (!be[0])

This causing a problem in a specific corner case. The following conditions need to met:

- You have a bus in your env with byte enable feature, for example APB

- You have a register in your design which have a register field which crossing a byte enable border, for example in a 16 bit register there is a 16 bit width field

- In your env you monitor all your register accesses and the env calls the predict() function of the UVM register layer

- You do a write access with byte enable 2'b10 or 2'b01

In the above described scenario the following will happen:

- In case of byte enable 2b'01:

 In the DUT only the LSB byte will be written but in the register layer the whole field will be updated

- In case of 2b'10:

In the DUT the MSB byte will be written but in the register layer the register field will not be updated at all

In both cases the contents of the register in the RTL and in the UVM register layer will be different. I think UVM should not assume that the entire register field is enabled or not. It should check if the entire field enabled or just part of it. I think it is a bug in the UVM package.

Can you please confirm this is a bug? If so, is this bug known for the developers? If not, how can I open a bug report for it in Mantis?



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