mparinda Posted January 19, 2012 Report Share Posted January 19, 2012 I'm trying to do random reset tests in OVM. The idea is that reset can happen any state. The problem is how do I have the on-going sequences aware of reset? For example, transaction package has A which drives 8 at reset. A can only be changed when A_en is 0. In a test, a sequence that has this transaction package, A changes its value from 8 -> 9 -> 10, etc.. Right before reset happens A was 15 and A_en is 1. During reset, the driver drives A = 8, A_en = 0 which are correct. But when reset is deasserted A_en goes to 1 and A goes to 15. This is because the on-going sequence is not aware of reset. How do I make the on-going sequence aware of reset? Quote Link to comment Share on other sites More sharing options...
SeanChou Posted January 31, 2012 Report Share Posted January 31, 2012 If there is only one seuqnce, you could let it control the reset pin and the problem is solved. Or if there are multiple sequences, you are actually finding some syncrhronization mechanism betwee sequences, there are uvm_objection or uvm_phase in bcl. Quote Link to comment Share on other sites More sharing options...
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