ViVo Posted February 27, 2018 Report Posted February 27, 2018 Hi, I'm trying to write generic 3-state buffer with method of the module as follows: note that 'output' is an sc_signal_rv<n> defined in the module's body. The problem is that the red section fails compilation because bit accessing is prohibited. Is the other way to set "all Z" when the resolved-signal width is a parameter n???? hope someone can help... V template <class T1, unsigned n, class T3> void bus3state_unit<T1,n,T3>::thread0(void) { T1 input ; input = in.read() ; for(int i=0;i<n;i++) output.write('Z') ; if( enable.read() ) { output.write(input) ; } out.write(output) ;} Quote
Roman Popov Posted February 27, 2018 Report Posted February 27, 2018 Do you mean you have : Quote sc_signal_rv<W> output{"output"}; ... output.write('Z'); This will compile: sc_signal_rv<W>::write takes sc_lv<W> as a parameter, that can be implicitly constructed from int. So your 'Z' (ASCII code 90) will be converted to int 90, that is probably not what you wanted. Quote
ViVo Posted February 27, 2018 Author Report Posted February 27, 2018 Hi Roman, thnx for the promptly reply. My Module looks like this: template <class T1, unsigned n, class T3> SC_MODULE(bus3state_unit) { /* -----------Input Ports--------------------------------------------------------- */ sc_in <T3> enable ; sc_in <T1> in ; /* -----------Output Ports-------------------------------------------------------- */ sc_out_rv<n> out ; /* -----------Input/Output Ports-------------------------------------------------- */ /* -----------Local Signal Declarations------------------------------------------- */ sc_signal_rv<n> output ; /* -----------Internal modules / variables---------------------------------------- */ /* -----------Methods------------------------------------------------------------- */ void thread0(void) ; /* -----------Constructor--------------------------------------------------------- */ SC_CTOR(bus3state_unit) : enable("enable"), in("in"), out("out") { char ii_str[20] ; SC_METHOD(thread0) ; dont_initialize() ; sensitive << enable ; /* -----------Open VCD file--------------------------------------------------- */ #ifdef BUS3STATE_UNIT std::string sname ; MDL_HIER2_NM(sc_core::sc_module,sname) ; wf = sc_create_vcd_trace_file(sname.c_str()) ; /* -----------Dump the desired signals---------------------------------------- */ sc_trace( wf, enable , "enable" ) ; sc_trace( wf, in , "in" ) ; sc_trace( wf, out , "out" ) ; #endif } private: sc_trace_file *wf ; } ; i'm not familiar with the notations: 1. sc_signal_rv<W> output{"output"}; 2. sc_signal_rv<W>::write is it a function?? V Quote
Roman Popov Posted February 27, 2018 Report Posted February 27, 2018 I just wanted to say that you code compiles, just probably won't do what you expect, because char 'Z' will be implicitly casted to int. In case you have compiler errors, please post them here. Quote
ViVo Posted February 27, 2018 Author Report Posted February 27, 2018 True, it compiles... but it do not act as it supposed to.. whats wrong? from what i read on sc_signal_rv<n> it should be used in situations that two writers may write to the same signal (bus in my case). i figured that all member functions of sc_signal_rv<n> class are all implemented by SC, is it not the case? V Quote
Roman Popov Posted February 27, 2018 Report Posted February 27, 2018 Most likely the problem is that you don't have enough expertise in C++. SystemC is rather advanced C++ library, so should read a good C++ book before approaching SystemC. Try to understand what is the difference between "Z" and 'Z' (notice quotation marks). Also read sc_signal_rv documentation in SystemC standard pdf. Here is a small example to show how sc_signal_rv works: #include <systemc.h> struct test : sc_module { sc_signal_rv<4> sig_rv{"sig_rv"}; SC_CTOR(test) { SC_THREAD(test_thread0); SC_THREAD(test_thread1); } void test_thread0 () { sig_rv = "Z10Z"; wait(1,SC_NS); cout << sig_rv << endl; } void test_thread1 () { sig_rv = "Z0Z1"; } }; int sc_main(int argc, char **argv) { test t0{"t0"}; sc_start(); return 0; } Quote
ViVo Posted February 28, 2018 Author Report Posted February 28, 2018 Hi Roman, trying to run this example, a compilation error pops for the line: sc_signal_rv<4> sig_rv{"sig_rv"}; error C2473: 'sig_rv' : looks like a function definition, but there is no parameter list. another error for the line : test t0{"t0"}; error C2601: 't0' : local function definitions are illegal any idea? another follow up questions, taking the example for bus-size n, how could you write instead of line : sig_rv = "Z0Z1"; something like: sig_rv = "Z..Z"; to signify n times "Z"? V Quote
Shashidhar Posted February 28, 2018 Report Posted February 28, 2018 Hi Vivo Probably your using older version of Gcc compiler or Visual Studio compiler test t0{"t0"}; this notation is supported in C++11 compiler onwards try instead test t0("t0"); Regards Shashidhar Quote
Shashidhar Posted February 28, 2018 Report Posted February 28, 2018 you can find a simple example on how to use sc resolved vector here http://www.asic-world.com/systemc/ports_signals4.html#Example_:_Resolved_Vector_Signals Sorry for the multiple posts Quote
ViVo Posted February 28, 2018 Author Report Posted February 28, 2018 Hi Shashidhar, altering the basic example of asic-world to accommodate two buffers wired at their outputs actually works. see the picture. 1. it seems that initially i used the sc_signal_rv<4> as member signal in a wrong way.. i will try to understand why.. 2. how can i write parametric number of 3states? for example instead of out.write("ZZZZ") something like out.write("Z",4) obviously this is something that most developers should encounter..? V Quote
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