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  1. Hi Shashidhar, altering the basic example of asic-world to accommodate two buffers wired at their outputs actually works. see the picture. 1. it seems that initially i used the sc_signal_rv<4> as member signal in a wrong way.. i will try to understand why.. 2. how can i write parametric number of 3states? for example instead of out.write("ZZZZ") something like out.write("Z",4) obviously this is something that most developers should encounter..? V
  2. Hi Roman, trying to run this example, a compilation error pops for the line: sc_signal_rv<4> sig_rv{"sig_rv"}; error C2473: 'sig_rv' : looks like a function definition, but there is no parameter list. another error for the line : test t0{"t0"}; error C2601: 't0' : local function definitions are illegal any idea? another follow up questions, taking the example for bus-size n, how could you write instead of line : sig_rv = "Z0Z1"; something like: sig_rv = "Z..Z"; to signify n times "Z"? V
  3. True, it compiles... but it do not act as it supposed to.. whats wrong? from what i read on sc_signal_rv<n> it should be used in situations that two writers may write to the same signal (bus in my case). i figured that all member functions of sc_signal_rv<n> class are all implemented by SC, is it not the case? V
  4. Hi Roman, thnx for the promptly reply. My Module looks like this: template <class T1, unsigned n, class T3> SC_MODULE(bus3state_unit) { /* -----------Input Ports--------------------------------------------------------- */ sc_in <T3> enable ; sc_in <T1> in ; /* -----------Output Ports-------------------------------------------------------- */ sc_out_rv<n>
  5. Hi, I'm trying to write generic 3-state buffer with method of the module as follows: note that 'output' is an sc_signal_rv<n> defined in the module's body. The problem is that the red section fails compilation because bit accessing is prohibited. Is the other way to set "all Z" when the resolved-signal width is a parameter n???? hope someone can help... V template <class T1, unsigned n, class T3> void bus3state_unit<T1,n,T3>::thread0(void) { T1 input ;
  6. So, windows is not functioning well ? i'm searching for stable environment for systemc, windows isn't sufficient ? what should i do ? V
  7. Hello Roman, thank you very much for your help.. i revised my code style upon your inputs.. As 1st step, i'm converting to the "recommended" sytle tammed in the "SystemC from the ground up" book. As shown in the attached files... The problem is that i get lots of errors saying: "template is illigal". Can i use this code style with parameterized module-type? BR, V basic_process_ex.cpp basic_process_ex.h main.cpp
  8. i wrote very simple template module (select_unit.h) with vector as one of its 3rd argument. i encounter difficulty instantiating it in the upper "floor" (up_mod.h). the marked red code should be the definition of std::vector of unsigned integers (template's 3rd parameter in select_unit module). the compiler complains for const 3rd argument..., how should i define the vector? any help would be appreciated. V. select_unit.h template <unsigned w_bus,unsigned w_sel, std::vector<unsigned> &sel_bits> SC_MODULE(select_unit) { /* --------
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