Shashidhar

you can find a simple example on how to use sc resolved vector here http://www.asic-world.com/systemc/ports_signals4.html#Example_:_Resolved_Vector_Signals Sorry for the multiple posts

Hi Vivo Probably your using older version of Gcc compiler or Visual Studio compiler test t0{"t0"}; this notation is supported in C++11 compiler onwards try instead test t0("t0"); Regards Shashidhar

Hi Ameya I have gone through the the link which you mentioned. if my understanding is correct,since simple sockets derive from standard sockets (tlm_initiator and target sockets) and these standard sockets are Inter operable ,so even simple sockets also supports interoperability. Regards Shashidhar

thanks for the link ameya. Any idea about my 2nd doubt?? 2)And also simple_initiator_socket is part of tlm_utils and the feature which are part of tlm_utils does not support inter operable ,I would like to know why??

HI 1)I would like to know the difference between tlm_initiator_socket and simple_initiator_socket. From TLM LRM ,I understood that simple_initiator_socket. is also derived from tlm_initiator_socket and we need to register this socket with nb_transport_bw in the constructor. But after from this,is there any advantages of using it over tlm_initiator_socke. 2)And also simple_initiator_socket is part of tlm_utils and the feature which are part of tlm_utils does not support inter operable ,I would like to know why?? Regards Shashidhar

Hi I have doubt about TLM Phase. Do i need use tlm phase in this specific order always (BEGIN_REQ,END_REQ,BEGIN_RESP and END_RESP)?? And if yes, what should be done when I send a BEGIN_REQ from the master side but get END_RESP from the slave side. (Should just stop the transaction??) Please help me out with this doubt