Roman Popov Posted January 10, 2018 Report Share Posted January 10, 2018 Verilog is currently supported by all major FPGA and ASIC synthesis vendors. This is why all other HDLs build on top of general purpose programming language offer Verilog converters. Verilog conversion is supported by Chisel (Scala), MyHDL (Python), CλaSH (Haskell). But there is no one for SystemC. This I think is a serious issue for SystemC adaption as hardware design language. Especially in academia, where students are generally using free tools for learning, like free versions of FPGA design suites. Quote Link to comment Share on other sites More sharing options...
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