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UVM run time phases

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Hi Guys,

I'm new to new. I have a doubet in my mind regarding uvm run_time phases reset, configure and main phase. Does we overwrite these run phases. When I tries to overwrite these phases , simulator never comes to my modifed task,Always it simulates the run task and main task I'm unable to execute pre_reset_phase, in which i want to add delay. Please provide the solution to this problem.

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