amitrana Posted December 19, 2011 Report Share Posted December 19, 2011 Hi Guys, I'm new to new. I have a doubet in my mind regarding uvm run_time phases reset, configure and main phase. Does we overwrite these run phases. When I tries to overwrite these phases , simulator never comes to my modifed task,Always it simulates the run task and main task I'm unable to execute pre_reset_phase, in which i want to add delay. Please provide the solution to this problem. Quote Link to comment Share on other sites More sharing options...
mbowler Posted December 19, 2011 Report Share Posted December 19, 2011 Are you raising an objection in the phase code? If you do not raise an objection, the phase will terminate immediately. Quote Link to comment Share on other sites More sharing options...
amitrana Posted December 20, 2011 Author Report Share Posted December 20, 2011 Yes I'm raising the objection from pre_reset_phase but ,never comes to this task .alwayas complete the run and main phase .I'm confused, does i need some extra switch. Quote Link to comment Share on other sites More sharing options...
mbowler Posted December 21, 2011 Report Share Posted December 21, 2011 Maybe if you post the component code we could see what you are doing wrong. Quote Link to comment Share on other sites More sharing options...
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